"Howard C. Berkowitz" wrote:
>
> >The thing is, Juniper's technology is based upon a central bus architecture
>
> shared memory, not shared bus. There is a difference. I don't
> have the URL handy, but Cisco has a paper out by the Stanford
> University professor who architected the GSR. It does a nice
> comparison of the three basic architectures, shared bus, shared
> memory, and crossbar. Shared bus runs out of steam at about 2Gbps,
> and the 7500 is about the highest end Cisco product that uses it.
> Junipers are generally shared memory and GSRs are generally crossbar.
And Catalyst layer 3 forwarders (dare I say routers?) use the shared
memory design, with some added wrinkles for QoS.
(hoping not to get the hair up on the back of Howard's neck re terminology...)
>
>where as the new GSR routers have a processor for each interface card (as
>the Juniper has one central CPU).
>
Rather than get hung up on how many "processors" and what that means, I
prefer to compare them functionally the way Howard has espoused here
before. There's a path determination function (software in some kind
of processor/CPU) and there's a packet forwarding function. The latter
can be done by line cards with their own CPUs, line cards with ASICs,
or other hardware-assisted implementations. Now when an interface flaps
or the path determination function gains or loses a prefix, what happens
and which components are involved?
- Marty
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