On Mon, Aug 25, 2003 at 02:29:53PM -0400, John Dennis wrote: >I have spent quite a bit of time investigating this issue and I think >we now understand the underlying issue. > >The various places in XFree86 that mmap memory seem to very careful to >specify the proper mapping attributes, e.g. when mapping registers >with ordering requirements and side-effects (e.g. MMIO) the mapping is >forced to be non-cached and ordered. But ROM (e.g. device bios) can be >read cached, it has no side-effects. Thus when xf86ReadBIOS maps the >ROM BIOS it does not force a non-cached mapping. In theory this is >correct. > >However on IA64 the concept of caching is overloaded, not only does it >refer to memory coherence but more importantly selects between two >vastly different memory spaces, RAM and IO. A cached access is >directed to RAM and a non-cached access is directed to IO (e.g. a pci >device).
Does this mean that the video memory aperture on a PCI device is classified as RAM, or is there something else that ensures that cached accesses get directed to the PCI device in this case? Is the difference that this is a writeable region while the ROM is read-only? David -- David Dawes Founder/committer/developer The XFree86 Project www.XFree86.org/~dawes _______________________________________________ Devel mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/devel
