Hi Ralph
On 08/09/10 08:42, Ralph Corderoy wrote:
Hi Tim,
Generated code looks OK
Something I used to find gcc didn't cope too well with when targetting
ARM was the C idiom `!!x' to map 0 onto 0, and everything else onto 1.
IOW, `x ? 1 : 0'.
For
signed int nnsi( int x) { return !!x; }
unsigned int nnui(unsigned int x) { return !!x; }
signed int tosi( int x) { return x ? 1 : 0; }
unsigned int toui(unsigned int x) { return x ? 1 : 0; }
this gcc with -O3 produces the same x86 for all four,
pushl %ebp
xorl %eax, %eax
movl %esp, %ebp
cmpl $0, 8(%ebp)
popl %ebp
setne %al
ret
I think ARM needs two instructions, ignoring function prologue and
epilogue,
teq r0, #0 ; nflag, zflag = r0 xor 0
movne r0, #1 ; if not zflag: r0 = 1
; else: r0 already 0
On Coldfire V1 it's coming up with
86 0030 4AAE 0008 tst.l 8(%fp)
87 0034 56C0 sne %d0
88 0036 4E5E unlk %fp
89 .cfi_offset 14, -8
90 0038 7100 mvs.b %d0,%d0
91 003a 4480 neg.l %d0
92 003c 4E75 rts
At first glance not sure why the mvs.b is necessary.
Cheers
Tim
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