I tried to get the 3rd TMU working on radeon,
and with this patch it works at least
without hw-TCL for multiarb.c from Mesa/demos.
(RADEON_TCL_FORCE_DISABLE=1)
With hw-TCL the 3rd texture is visible, but
isnt rotating.
The patch also includes some code for the
kernelmodule for cube-textures on radeon,
and some comments where I dont know what to do.
You can switch off the 3rd TMU with export RADEON_NO_3RD_TMU=1
It would be nice if someone with knowledge about
TCL could have a look at it.
Which programs/demos/games could/should be tested as
they make use of the 3rd texture unit?
best regards,
Andreas
diff -ru current_trunk/xc/xc/extras/Mesa/src/tnl_dd/t_dd_vbtmp.h tex3_20030619/xc/xc/extras/Mesa/src/tnl_dd/t_dd_vbtmp.h
--- current_trunk/xc/xc/extras/Mesa/src/tnl_dd/t_dd_vbtmp.h Fri Apr 4 19:31:02 2003
+++ tex3_20030619/xc/xc/extras/Mesa/src/tnl_dd/t_dd_vbtmp.h Thu Jun 19 20:44:25 2003
@@ -404,6 +404,20 @@
v->v.v1 = tc1[i][1];
}
}
+ if (DO_TEX2) {
+ if (DO_PTEX) {
+ v->pv.u2 = tc2[i][0];
+ v->pv.v2 = tc2[i][1];
+ if (tc2_size == 4)
+ v->pv.q2 = tc2[i][3];
+ else
+ v->pv.q2 = 1.0;
+ }
+ else {
+ v->v.u2 = tc2[i][0];
+ v->v.v2 = tc2[i][1];
+ }
+ }
}
}
}
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.c Wed Jun 11 00:06:16 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.c Sat Jun 21 13:35:01 2003
@@ -301,7 +301,10 @@
*/
ctx = rmesa->glCtx;
- ctx->Const.MaxTextureUnits = 2;
+ if( (sPriv->drmMinor < 3) || (getenv( "RADEON_NO_3RD_TMU")) ) /* question: is the check for drmMinor necessary? */
+ ctx->Const.MaxTextureUnits = 2;
+ else
+ ctx->Const.MaxTextureUnits = RADEON_MAX_TEXTURE_UNITS; /* 3 */
driCalculateMaxTextureLevels( rmesa->texture_heaps,
rmesa->nr_heaps,
@@ -374,13 +377,15 @@
_math_matrix_ctr( &rmesa->TexGenMatrix[0] );
_math_matrix_ctr( &rmesa->TexGenMatrix[1] );
+ _math_matrix_ctr( &rmesa->TexGenMatrix[2] );
_math_matrix_ctr( &rmesa->tmpmat );
_math_matrix_set_identity( &rmesa->TexGenMatrix[0] );
_math_matrix_set_identity( &rmesa->TexGenMatrix[1] );
+ _math_matrix_set_identity( &rmesa->TexGenMatrix[2] );
_math_matrix_set_identity( &rmesa->tmpmat );
driInitExtensions( ctx, card_extensions, GL_TRUE );
- if( rmesa->dri.drmMinor >= 9 || getenv( "RADEON_RECTANGLE_FORCE_ENABLE")) /* FIXME! a.s. */
+ if( rmesa->dri.drmMinor >= 9)
_mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
radeonInitDriverFuncs( ctx );
radeonInitIoctlFuncs( ctx );
@@ -416,6 +421,8 @@
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
}
+ /* question: shouldn't the following be controlled by the kernelmodule */
+ /* and/or Xserver-configuration if it can crash the card? */
else if (getenv("RADEON_TCL_FORCE_ENABLE")) {
fprintf(stderr, "Enabling TCL support... this will probably crash\n");
fprintf(stderr, " your card if it isn't capable of TCL!\n");
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h Wed Jun 11 00:06:16 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h Sat Jun 21 12:34:11 2003
@@ -129,7 +129,8 @@
#define TEX_0 0x1
#define TEX_1 0x2
-#define TEX_ALL 0x3
+#define TEX_2 0x4
+#define TEX_ALL 0x7
typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
@@ -260,10 +261,20 @@
#define TEX_STATE_SIZE 9
#define TXR_CMD_0 0 /* rectangle textures */
-#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */
-#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */
+#define TXR_PP_TEX_SIZE 1 /* for NPOT */
+#define TXR_PP_TEX_PITCH 2 /* for NPOT */
#define TXR_STATE_SIZE 3
+#define CUBE_CMD_0 0
+#define CUBE_PP_CUBIC_FACES 1
+#define CUBE_CMD_1 2
+#define CUBE_PP_CUBIC_OFFSET_0 3 /* question: this looks a bit strange for radeon */
+#define CUBE_PP_CUBIC_OFFSET_1 4 /* (_0.._4) compared to r200 (_F1.._F5) */
+#define CUBE_PP_CUBIC_OFFSET_2 5 /* could someone clarify which offset belongs to */
+#define CUBE_PP_CUBIC_OFFSET_3 6 /* which face? */
+#define CUBE_PP_CUBIC_OFFSET_4 7
+#define CUBE_STATE_SIZE 8
+
#define ZBS_CMD_0 0
#define ZBS_SE_ZBIAS_FACTOR 1
#define ZBS_SE_ZBIAS_CONSTANT 2
@@ -417,17 +428,18 @@
struct radeon_state_atom vpt;
struct radeon_state_atom tcl;
struct radeon_state_atom msc;
- struct radeon_state_atom tex[2];
+ struct radeon_state_atom tex[3]; /* RADEON_MAX_TEXTURE_UNITS */
+ struct radeon_state_atom txr[3]; /* RADEON_MAX_TEXTURE_UNITS, for NPOT */
+ struct radeon_state_atom cube[3]; /* RADEON_MAX_TEXTURE_UNITS */
struct radeon_state_atom zbs;
struct radeon_state_atom mtl;
- struct radeon_state_atom mat[5];
+ struct radeon_state_atom mat[6]; /* 3 + RADEON_MAX_TEXTURE_UNITS */
struct radeon_state_atom lit[8]; /* includes vec, scl commands */
struct radeon_state_atom ucp[6];
struct radeon_state_atom eye; /* eye pos */
struct radeon_state_atom grd; /* guard band clipping */
struct radeon_state_atom fog;
struct radeon_state_atom glt;
- struct radeon_state_atom txr[2]; /* for NPOT */
};
struct radeon_state {
@@ -635,30 +647,35 @@
GLuint prim;
};
+#define RADEON_MAX_VERTEX_SIZE 17
+
struct radeon_vbinfo {
GLint counter, initial_counter;
GLint *dmaptr;
void (*notify)( void );
GLint vertex_size;
- /* A maximum total of 15 elements per vertex: 3 floats for position, 3
+ /* A maximum total of 17 elements per vertex: 3 floats for position, 3
* floats for normal, 4 floats for color, 4 bytes for secondary color,
- * 2 floats for each texture unit (4 floats total).
+ * 2 floats for each texture unit (6 floats total).
*
- * As soon as the 3rd TMU is supported or cube maps (or 3D textures) are
+ * As soon as cube maps (or 3D textures) are
* supported, this value will grow.
*
* The position data is never actually stored here, so 3 elements could be
* trimmed out of the buffer.
*/
- union { float f; int i; radeon_color_t color; } vertex[15];
+ union { float f; int i; radeon_color_t color; } vertex[RADEON_MAX_VERTEX_SIZE];
GLfloat *normalptr;
GLfloat *floatcolorptr;
radeon_color_t *colorptr;
GLfloat *floatspecptr;
radeon_color_t *specptr;
- GLfloat *texcoordptr[2];
+ GLfloat *texcoordptr[4]; /* this should be RADEON_MAX_TEXTURE_UNITS but */
+ /* the extra one is needed in radeon_vtxfmt_c.c if */
+ /* someone specifies GL_TEXTURE3 */
+ /* maybe we should just use mesas MAX_TEXTURE_UNITS here */
GLenum *prim; /* &ctx->Driver.CurrentExecPrimitive */
GLuint primflags;
@@ -804,6 +821,10 @@
}
}
+/* FIXME: RADEON_OLD_PACKETS was set to 0 during the tcl-0-0-branch work/merge but */
+/* was reverted to be 1 about three weeks later because of problems */
+/* when buffer wraps between packets. */
+/* question: Are the problems fixed now elsewhere ? */
#define RADEON_OLD_PACKETS 1
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c Wed Jun 11 00:06:17 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c Thu Jun 19 14:02:42 2003
@@ -422,7 +422,7 @@
cmd[0].i = 0;
cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
- cmd[1].i = RADEON_CP_PACKET3_CNTL_BITBLT_MULTI | (5 << 16); /* FIXME: is this the right package? */
+ cmd[1].i = RADEON_CP_PACKET3_CNTL_BITBLT_MULTI | (5 << 16);
cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_NONE |
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_arrays.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_arrays.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_arrays.c Fri May 2 13:01:53 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_arrays.c Thu Jun 19 14:02:42 2003
@@ -514,7 +514,7 @@
}
vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &
- ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1));
+ ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1|RADEON_TCL_VTX_Q2));
if (inputs & VERT_BIT_TEX0) {
if (!rmesa->tcl.tex[0].buf)
@@ -554,6 +554,25 @@
component[nr++] = &rmesa->tcl.tex[1];
}
+ if (inputs & VERT_BIT_TEX2) {
+ if (!rmesa->tcl.tex[2].buf)
+ emit_tex_vector( ctx,
+ &(rmesa->tcl.tex[2]),
+ (char *)VB->TexCoordPtr[2]->data,
+ VB->TexCoordPtr[2]->size,
+ VB->TexCoordPtr[2]->stride,
+ count );
+
+ switch( VB->TexCoordPtr[2]->size ) {
+ case 4:
+ vtx |= RADEON_TCL_VTX_Q2;
+ vfmt |= RADEON_CP_VC_FRMT_Q2;
+ default:
+ vfmt |= RADEON_CP_VC_FRMT_ST2;
+ }
+ component[nr++] = &rmesa->tcl.tex[2];
+ }
+
if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) {
RADEON_STATECHANGE( rmesa, tcl );
rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx;
@@ -588,4 +607,7 @@
if (newinputs & VERT_BIT_TEX1)
radeonReleaseDmaRegion( rmesa, &rmesa->tcl.tex[1], __FUNCTION__ );
+
+ if (newinputs & VERT_BIT_TEX2)
+ radeonReleaseDmaRegion( rmesa, &rmesa->tcl.tex[2], __FUNCTION__ );
}
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_vbtmp.h tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_vbtmp.h
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_vbtmp.h Mon Nov 25 21:20:09 2002
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_vbtmp.h Sat Jun 21 09:56:38 2003
@@ -31,7 +31,7 @@
#undef TCL_DEBUG
#ifndef TCL_DEBUG
-#define TCL_DEBUG 0
+#define TCL_DEBUG (RADEON_DEBUG) /* FIXME: change this back to 0 before merging */
#endif
static void TAG(emit)( GLcontext *ctx,
@@ -78,14 +78,19 @@
coord_stride = VB->ObjPtr->stride;
if (DO_TEX2) {
- const GLuint t2 = GET_TEXSOURCE(2);
- tc2 = (GLuint (*)[4])VB->TexCoordPtr[t2]->data;
- tc2_stride = VB->TexCoordPtr[t2]->stride;
- if (DO_PTEX && VB->TexCoordPtr[t2]->size < 4) {
- if (VB->TexCoordPtr[t2]->flags & VEC_NOT_WRITEABLE) {
- VB->import_data( ctx, VERT_BIT_TEX2, VEC_NOT_WRITEABLE );
+ if (VB->TexCoordPtr[2]) {
+ const GLuint t2 = GET_TEXSOURCE(2);
+ tc2 = (GLuint (*)[4])VB->TexCoordPtr[t2]->data;
+ tc2_stride = VB->TexCoordPtr[t2]->stride;
+ if (DO_PTEX && VB->TexCoordPtr[t2]->size < 4) {
+ if (VB->TexCoordPtr[t2]->flags & VEC_NOT_WRITEABLE) {
+ VB->import_data( ctx, VERT_BIT_TEX2, VEC_NOT_WRITEABLE );
+ }
+ _mesa_vector4f_clean_elem( VB->TexCoordPtr[t2], VB->Count, 3 );
}
- _mesa_vector4f_clean_elem( VB->TexCoordPtr[t2], VB->Count, 3 );
+ } else {
+ tc2 = (GLuint (*)[4])&ctx->Current.Attrib[VERT_ATTRIB_TEX2]; /* could be anything, really */
+ tc2_stride = 0;
}
}
@@ -263,8 +268,10 @@
if (DO_TEX2) {
v[0].ui = tc2[0][0];
v[1].ui = tc2[0][1];
+ if (TCL_DEBUG) fprintf(stderr, "t2: %.2f %.2f ", v[0].f, v[1].f);
if (DO_PTEX) {
v[2].ui = tc2[0][3];
+ if (TCL_DEBUG) fprintf(stderr, "%.2f ", v[2].f);
v += 3;
}
else
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_verts.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_verts.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_verts.c Fri May 2 13:01:53 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_verts.c Fri Jun 20 22:01:18 2003
@@ -51,7 +51,7 @@
#include "radeon_maos.h"
-#define RADEON_TCL_MAX_SETUP 13
+#define RADEON_TCL_MAX_SETUP 19
union emit_union { float f; GLuint ui; radeon_color_t specular; };
@@ -67,10 +67,10 @@
#define DO_FOG (IND & RADEON_CP_VC_FRMT_PKSPEC)
#define DO_TEX0 (IND & RADEON_CP_VC_FRMT_ST0)
#define DO_TEX1 (IND & RADEON_CP_VC_FRMT_ST1)
+#define DO_TEX2 (IND & RADEON_CP_VC_FRMT_ST2)
#define DO_PTEX (IND & RADEON_CP_VC_FRMT_Q0)
#define DO_NORM (IND & RADEON_CP_VC_FRMT_N0)
-#define DO_TEX2 0
#define DO_TEX3 0
#define GET_TEXSOURCE(n) n
@@ -207,6 +207,81 @@
#define TAG(x) x##_w_rgpa_spec_stq_stq_n
#include "radeon_maos_vbtmp.h"
+/* FIXME: someone should check if the ordering is right or */
+/* if we can eliminate some of them or */
+/* if it could help some programs to have some more */
+#define IDX 13
+#define IND (RADEON_CP_VC_FRMT_XY| \
+ RADEON_CP_VC_FRMT_Z| \
+ RADEON_CP_VC_FRMT_PKCOLOR| \
+ RADEON_CP_VC_FRMT_ST0| \
+ RADEON_CP_VC_FRMT_ST1| \
+ RADEON_CP_VC_FRMT_ST2)
+#define TAG(x) x##_rgba_st_st_st
+#include "radeon_maos_vbtmp.h"
+
+#define IDX 14
+#define IND (RADEON_CP_VC_FRMT_XY| \
+ RADEON_CP_VC_FRMT_Z| \
+ RADEON_CP_VC_FRMT_PKCOLOR| \
+ RADEON_CP_VC_FRMT_PKSPEC| \
+ RADEON_CP_VC_FRMT_ST0| \
+ RADEON_CP_VC_FRMT_ST1| \
+ RADEON_CP_VC_FRMT_ST2)
+#define TAG(x) x##_rgba_spec_st_st_st
+#include "radeon_maos_vbtmp.h"
+
+#define IDX 15
+#define IND (RADEON_CP_VC_FRMT_XY| \
+ RADEON_CP_VC_FRMT_Z| \
+ RADEON_CP_VC_FRMT_ST0| \
+ RADEON_CP_VC_FRMT_ST1| \
+ RADEON_CP_VC_FRMT_ST2| \
+ RADEON_CP_VC_FRMT_N0)
+#define TAG(x) x##_st_st_st_n
+#include "radeon_maos_vbtmp.h"
+
+#define IDX 16
+#define IND (RADEON_CP_VC_FRMT_XY| \
+ RADEON_CP_VC_FRMT_Z| \
+ RADEON_CP_VC_FRMT_PKCOLOR| \
+ RADEON_CP_VC_FRMT_PKSPEC| \
+ RADEON_CP_VC_FRMT_ST0| \
+ RADEON_CP_VC_FRMT_ST1| \
+ RADEON_CP_VC_FRMT_ST2| \
+ RADEON_CP_VC_FRMT_N0)
+#define TAG(x) x##_rgpa_spec_st_st_st_n
+#include "radeon_maos_vbtmp.h"
+
+#define IDX 17
+#define IND (RADEON_CP_VC_FRMT_XY| \
+ RADEON_CP_VC_FRMT_Z| \
+ RADEON_CP_VC_FRMT_PKCOLOR| \
+ RADEON_CP_VC_FRMT_ST0| \
+ RADEON_CP_VC_FRMT_Q0| \
+ RADEON_CP_VC_FRMT_ST1| \
+ RADEON_CP_VC_FRMT_Q1| \
+ RADEON_CP_VC_FRMT_ST2| \
+ RADEON_CP_VC_FRMT_Q2)
+#define TAG(x) x##_rgba_stq_stq_stq
+#include "radeon_maos_vbtmp.h"
+
+#define IDX 18
+#define IND (RADEON_CP_VC_FRMT_XY| \
+ RADEON_CP_VC_FRMT_Z| \
+ RADEON_CP_VC_FRMT_W0| \
+ RADEON_CP_VC_FRMT_PKCOLOR| \
+ RADEON_CP_VC_FRMT_PKSPEC| \
+ RADEON_CP_VC_FRMT_ST0| \
+ RADEON_CP_VC_FRMT_Q0| \
+ RADEON_CP_VC_FRMT_ST1| \
+ RADEON_CP_VC_FRMT_Q1| \
+ RADEON_CP_VC_FRMT_ST2| \
+ RADEON_CP_VC_FRMT_Q2| \
+ RADEON_CP_VC_FRMT_N0)
+#define TAG(x) x##_w_rgpa_spec_stq_stq_stq_n
+#include "radeon_maos_vbtmp.h"
+
@@ -231,6 +306,12 @@
init_rgba_stq();
init_rgba_stq_stq();
init_w_rgpa_spec_stq_stq_n();
+ init_rgba_st_st_st();
+ init_rgba_spec_st_st_st();
+ init_st_st_st_n();
+ init_rgpa_spec_st_st_st_n(); /* question: don't know what "rgpa" is, just copied and modified.. */
+ init_rgba_stq_stq_stq();
+ init_w_rgpa_spec_stq_stq_stq_n();
}
@@ -283,6 +364,15 @@
if (VB->TexCoordPtr[1]->size == 4) {
req |= RADEON_CP_VC_FRMT_Q1;
vtx |= RADEON_TCL_VTX_Q1;
+ }
+ }
+
+ if (inputs & VERT_BIT_TEX2) {
+ req |= RADEON_CP_VC_FRMT_ST2;
+
+ if (VB->TexCoordPtr[2]->size == 4) {
+ req |= RADEON_CP_VC_FRMT_Q2;
+ vtx |= RADEON_TCL_VTX_Q2;
}
}
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_sanity.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_sanity.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_sanity.c Wed Jun 11 00:06:17 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_sanity.c Sat Jun 21 13:27:53 2003
@@ -136,7 +136,13 @@
{ 0, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
{ RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
- { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
+ { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
+ { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" },
+ { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
+ { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" },
+ { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
+ { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
+ { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
};
struct reg_names {
@@ -177,22 +183,22 @@
{ RADEON_PP_TXFILTER_2, "RADEON_PP_TXFILTER_2" },
{ RADEON_PP_TXFORMAT_0, "RADEON_PP_TXFORMAT_0" },
{ RADEON_PP_TXFORMAT_1, "RADEON_PP_TXFORMAT_1" },
- { RADEON_PP_TXFORMAT_2, "RADEON_PP_TXFORMAT_3" },
+ { RADEON_PP_TXFORMAT_2, "RADEON_PP_TXFORMAT_2" },
{ RADEON_PP_TXOFFSET_0, "RADEON_PP_TXOFFSET_0" },
{ RADEON_PP_TXOFFSET_1, "RADEON_PP_TXOFFSET_1" },
- { RADEON_PP_TXOFFSET_2, "RADEON_PP_TXOFFSET_3" },
+ { RADEON_PP_TXOFFSET_2, "RADEON_PP_TXOFFSET_2" },
{ RADEON_PP_TXCBLEND_0, "RADEON_PP_TXCBLEND_0" },
{ RADEON_PP_TXCBLEND_1, "RADEON_PP_TXCBLEND_1" },
- { RADEON_PP_TXCBLEND_2, "RADEON_PP_TXCBLEND_3" },
+ { RADEON_PP_TXCBLEND_2, "RADEON_PP_TXCBLEND_2" },
{ RADEON_PP_TXABLEND_0, "RADEON_PP_TXABLEND_0" },
{ RADEON_PP_TXABLEND_1, "RADEON_PP_TXABLEND_1" },
- { RADEON_PP_TXABLEND_2, "RADEON_PP_TXABLEND_3" },
+ { RADEON_PP_TXABLEND_2, "RADEON_PP_TXABLEND_2" },
{ RADEON_PP_TFACTOR_0, "RADEON_PP_TFACTOR_0" },
{ RADEON_PP_TFACTOR_1, "RADEON_PP_TFACTOR_1" },
- { RADEON_PP_TFACTOR_2, "RADEON_PP_TFACTOR_3" },
+ { RADEON_PP_TFACTOR_2, "RADEON_PP_TFACTOR_2" },
{ RADEON_PP_BORDER_COLOR_0, "RADEON_PP_BORDER_COLOR_0" },
{ RADEON_PP_BORDER_COLOR_1, "RADEON_PP_BORDER_COLOR_1" },
- { RADEON_PP_BORDER_COLOR_2, "RADEON_PP_BORDER_COLOR_3" },
+ { RADEON_PP_BORDER_COLOR_2, "RADEON_PP_BORDER_COLOR_2" },
{ RADEON_SE_ZBIAS_FACTOR, "RADEON_SE_ZBIAS_FACTOR" },
{ RADEON_SE_ZBIAS_CONSTANT, "RADEON_SE_ZBIAS_CONSTANT" },
{ RADEON_SE_TCL_OUTPUT_VTX_FMT, "RADEON_SE_TCL_OUTPUT_VTXFMT" },
@@ -227,9 +233,27 @@
{ RADEON_PP_TEX_SIZE_0, "RADEON_PP_TEX_SIZE_0" },
{ RADEON_PP_TEX_SIZE_1, "RADEON_PP_TEX_SIZE_1" },
{ RADEON_PP_TEX_SIZE_2, "RADEON_PP_TEX_SIZE_2" },
- { RADEON_PP_TEX_SIZE_0+4, "RADEON_PP_TEX_PITCH_0" },
- { RADEON_PP_TEX_SIZE_1+4, "RADEON_PP_TEX_PITCH_1" },
- { RADEON_PP_TEX_SIZE_2+4, "RADEON_PP_TEX_PITCH_2" },
+ { RADEON_PP_TEX_PITCH_0, "RADEON_PP_TEX_PITCH_0" },
+ { RADEON_PP_TEX_PITCH_1, "RADEON_PP_TEX_PITCH_1" },
+ { RADEON_PP_TEX_PITCH_2, "RADEON_PP_TEX_PITCH_2" },
+ { RADEON_PP_CUBIC_FACES_0, "RADEON_PP_CUBIC_FACES_0" },
+ { RADEON_PP_CUBIC_FACES_1, "RADEON_PP_CUBIC_FACES_1" },
+ { RADEON_PP_CUBIC_FACES_2, "RADEON_PP_CUBIC_FACES_2" },
+ { RADEON_PP_CUBIC_OFFSET_T0_0, "RADEON_PP_CUBIC_OFFSET_T0_0" },
+ { RADEON_PP_CUBIC_OFFSET_T0_1, "RADEON_PP_CUBIC_OFFSET_T0_1" },
+ { RADEON_PP_CUBIC_OFFSET_T0_2, "RADEON_PP_CUBIC_OFFSET_T0_2" },
+ { RADEON_PP_CUBIC_OFFSET_T0_3, "RADEON_PP_CUBIC_OFFSET_T0_3" },
+ { RADEON_PP_CUBIC_OFFSET_T0_4, "RADEON_PP_CUBIC_OFFSET_T0_4" },
+ { RADEON_PP_CUBIC_OFFSET_T1_0, "RADEON_PP_CUBIC_OFFSET_T1_0" },
+ { RADEON_PP_CUBIC_OFFSET_T1_1, "RADEON_PP_CUBIC_OFFSET_T1_1" },
+ { RADEON_PP_CUBIC_OFFSET_T1_2, "RADEON_PP_CUBIC_OFFSET_T1_2" },
+ { RADEON_PP_CUBIC_OFFSET_T1_3, "RADEON_PP_CUBIC_OFFSET_T1_3" },
+ { RADEON_PP_CUBIC_OFFSET_T1_4, "RADEON_PP_CUBIC_OFFSET_T1_4" },
+ { RADEON_PP_CUBIC_OFFSET_T2_0, "RADEON_PP_CUBIC_OFFSET_T2_0" },
+ { RADEON_PP_CUBIC_OFFSET_T2_1, "RADEON_PP_CUBIC_OFFSET_T2_1" },
+ { RADEON_PP_CUBIC_OFFSET_T2_2, "RADEON_PP_CUBIC_OFFSET_T2_2" },
+ { RADEON_PP_CUBIC_OFFSET_T2_3, "RADEON_PP_CUBIC_OFFSET_T2_3" },
+ { RADEON_PP_CUBIC_OFFSET_T2_4, "RADEON_PP_CUBIC_OFFSET_T2_4" },
};
static struct reg_names scalar_names[] = {
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state.c Tue Jun 10 11:58:47 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state.c Fri Jun 20 22:01:59 2003
@@ -1959,7 +1959,7 @@
rmesa->TexMatEnabled = 0;
- for (unit = 0 ; unit < 2; unit++) {
+ for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) {
if (!ctx->Texture.Unit[unit]._ReallyEnabled) {
}
else if (ctx->TextureMatrixStack[unit].Top->type != MATRIX_IDENTITY) {
@@ -1994,7 +1994,8 @@
tpc = (rmesa->TexMatEnabled | rmesa->TexGenEnabled);
vs &= ~((0xf << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
- (0xf << RADEON_TCL_TEX_1_OUTPUT_SHIFT));
+ (0xf << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
+ (0xf << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
if (tpc & RADEON_TEXGEN_TEXMAT_0_ENABLE)
vs |= RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT;
@@ -2005,6 +2006,11 @@
vs |= RADEON_TCL_TEX_COMPUTED_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT;
else
vs |= RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT;
+
+ if (tpc & RADEON_TEXGEN_TEXMAT_2_ENABLE)
+ vs |= RADEON_TCL_TEX_COMPUTED_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT;
+ else
+ vs |= RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT;
if (tpc != rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] ||
vs != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL]) {
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c Wed Jun 11 00:06:18 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c Fri Jun 20 22:19:03 2003
@@ -112,10 +112,20 @@
CHECK( always, GL_TRUE )
CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled )
CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled )
+CHECK( tex2, ctx->Texture.Unit[2]._ReallyEnabled )
+CHECK( txr0, ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT)
+CHECK( txr1, ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT)
+CHECK( txr2, ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT)
+CHECK( cube0, ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT)
+CHECK( cube1, ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT)
+CHECK( cube2, ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT)
+/* question: or should we do the check as its done in the r200 driver: */
+/* use a generic tex_all check for tex, txr, cube ? */
CHECK( fog, ctx->Fog.Enabled )
TCL_CHECK( tcl, GL_TRUE )
TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled )
TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled )
+TCL_CHECK( tcl_tex2, ctx->Texture.Unit[2]._ReallyEnabled )
TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled )
TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled )
@@ -134,9 +144,6 @@
TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) )
TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled )
-CHECK( txr0, ctx->Texture.Unit[0]._ReallyEnabled )
-CHECK( txr1, ctx->Texture.Unit[1]._ReallyEnabled )
-
/* Initialize the context's hardware state.
@@ -230,11 +237,19 @@
ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 );
ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 );
+ ALLOC_STATE( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0 );
+ ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 );
+ ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 );
+ ALLOC_STATE( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0 );
+ ALLOC_STATE( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0 );
+ ALLOC_STATE( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0 );
+ ALLOC_STATE( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0 );
ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 );
ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 );
+ ALLOC_STATE( mat[5], tcl_tex2, MAT_STATE_SIZE, "MAT/texmat2", 1 );
ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
@@ -249,8 +264,6 @@
ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
- ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 );
- ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 );
/* Fill in the packet headers:
@@ -269,12 +282,21 @@
rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_0);
rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_1);
rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_1);
+ rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_2);
+ rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_2);
+ rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0);
+ rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1);
+ rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_2);
+ rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_0);
+ rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T0);
+ rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_1);
+ rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T1);
+ rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_2);
+ rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T2);
rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR);
rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
rmesa->hw.mtl.cmd[MTL_CMD_0] =
cmdpkt(RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
- rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0);
- rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1);
rmesa->hw.grd.cmd[GRD_CMD_0] =
cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
rmesa->hw.fog.cmd[FOG_CMD_0] =
@@ -284,7 +306,7 @@
rmesa->hw.eye.cmd[EYE_CMD_0] =
cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 );
- for (i = 0 ; i < 5; i++) {
+ for (i = 0 ; i < 6; i++) {
rmesa->hw.mat[i].cmd[MAT_CMD_0] =
cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16);
}
@@ -417,12 +439,12 @@
rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
(RADEON_TXFORMAT_ENDIAN_NO_SWAP |
RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
- (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
+ (i << RADEON_TXFORMAT_ST_ROUTE_SHIFT) |
(2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
(2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
/* FIXME: What is this magic value? */
- rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = 0x2000 << (2 * i);
+ rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = 0x2000 << (2 * i); /* question: does anyone know? */
rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_swtcl.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_swtcl.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_swtcl.c Wed Jun 11 00:06:19 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_swtcl.c Fri Jun 20 22:26:19 2003
@@ -63,8 +63,9 @@
#define RADEON_SPEC_BIT 0x04
#define RADEON_TEX0_BIT 0x08
#define RADEON_TEX1_BIT 0x10
-#define RADEON_PTEX_BIT 0x20
-#define RADEON_MAX_SETUP 0x40
+#define RADEON_TEX2_BIT 0x20
+#define RADEON_PTEX_BIT 0x40
+#define RADEON_MAX_SETUP 0x80
static void flush_last_swtcl_prim( radeonContextPtr rmesa );
static void flush_last_swtcl_prim_compat( radeonContextPtr rmesa );
@@ -115,9 +116,28 @@
RADEON_CP_VC_FRMT_ST1 | \
RADEON_CP_VC_FRMT_Q1)
-#define TEX2_VERTEX_FORMAT 0
+#define TEX2_VERTEX_FORMAT (RADEON_CP_VC_FRMT_XY | \
+ RADEON_CP_VC_FRMT_Z | \
+ RADEON_CP_VC_FRMT_W0 | \
+ RADEON_CP_VC_FRMT_PKCOLOR | \
+ RADEON_CP_VC_FRMT_PKSPEC | \
+ RADEON_CP_VC_FRMT_ST0 | \
+ RADEON_CP_VC_FRMT_ST1 | \
+ RADEON_CP_VC_FRMT_ST2)
+
+#define PROJ_TEX3_VERTEX_FORMAT (RADEON_CP_VC_FRMT_XY | \
+ RADEON_CP_VC_FRMT_Z | \
+ RADEON_CP_VC_FRMT_W0 | \
+ RADEON_CP_VC_FRMT_PKCOLOR | \
+ RADEON_CP_VC_FRMT_PKSPEC | \
+ RADEON_CP_VC_FRMT_ST0 | \
+ RADEON_CP_VC_FRMT_Q0 | \
+ RADEON_CP_VC_FRMT_ST1 | \
+ RADEON_CP_VC_FRMT_Q1 | \
+ RADEON_CP_VC_FRMT_ST2 | \
+ RADEON_CP_VC_FRMT_Q2)
+
#define TEX3_VERTEX_FORMAT 0
-#define PROJ_TEX3_VERTEX_FORMAT 0
#define DO_XYZW (IND & RADEON_XYZW_BIT)
#define DO_RGBA (IND & RADEON_RGBA_BIT)
@@ -125,7 +145,7 @@
#define DO_FOG (IND & RADEON_SPEC_BIT)
#define DO_TEX0 (IND & RADEON_TEX0_BIT)
#define DO_TEX1 (IND & RADEON_TEX1_BIT)
-#define DO_TEX2 0
+#define DO_TEX2 (IND & RADEON_TEX2_BIT)
#define DO_TEX3 0
#define DO_PTEX (IND & RADEON_PTEX_BIT)
@@ -148,7 +168,7 @@
#define HAVE_NOTEX_VERTICES 1
#define HAVE_TEX0_VERTICES 1
#define HAVE_TEX1_VERTICES 1
-#define HAVE_TEX2_VERTICES 0
+#define HAVE_TEX2_VERTICES 1
#define HAVE_TEX3_VERTICES 0
#define HAVE_PTEX_VERTICES 1
@@ -194,10 +214,20 @@
#include "tnl_dd/t_dd_vbtmp.h"
#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT|\
+ RADEON_TEX2_BIT)
+#define TAG(x) x##_wgt0t1t2
+#include "tnl_dd/t_dd_vbtmp.h"
+
+#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT|\
RADEON_PTEX_BIT)
#define TAG(x) x##_wgpt0t1
#include "tnl_dd/t_dd_vbtmp.h"
+#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT|\
+ RADEON_TEX2_BIT|RADEON_PTEX_BIT)
+#define TAG(x) x##_wgpt0t1t2
+#include "tnl_dd/t_dd_vbtmp.h"
+
#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_SPEC_BIT)
#define TAG(x) x##_wgfs
#include "tnl_dd/t_dd_vbtmp.h"
@@ -218,10 +248,21 @@
#include "tnl_dd/t_dd_vbtmp.h"
#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_SPEC_BIT|\
+ RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_TEX2_BIT)
+#define TAG(x) x##_wgfst0t1t2
+#include "tnl_dd/t_dd_vbtmp.h"
+
+#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_SPEC_BIT|\
RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_PTEX_BIT)
#define TAG(x) x##_wgfspt0t1
#include "tnl_dd/t_dd_vbtmp.h"
+#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_SPEC_BIT|\
+ RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_TEX2_BIT|\
+ RADEON_PTEX_BIT)
+#define TAG(x) x##_wgfspt0t1t2
+#include "tnl_dd/t_dd_vbtmp.h"
+
/***********************************************************************
* Initialization
@@ -233,19 +274,23 @@
init_wgt0();
init_wgpt0();
init_wgt0t1();
+ init_wgt0t1t2();
init_wgpt0t1();
+ init_wgpt0t1t2();
init_wgfs();
init_wgfst0();
init_wgfspt0();
init_wgfst0t1();
+ init_wgfst0t1t2();
init_wgfspt0t1();
+ init_wgfspt0t1t2();
}
void radeonPrintSetupFlags(char *msg, GLuint flags )
{
- fprintf(stderr, "%s(%x): %s%s%s%s%s%s\n",
+ fprintf(stderr, "%s(%x): %s%s%s%s%s%s%s\n",
msg,
(int)flags,
(flags & RADEON_XYZW_BIT) ? " xyzw," : "",
@@ -253,6 +298,7 @@
(flags & RADEON_SPEC_BIT) ? " spec/fog," : "",
(flags & RADEON_TEX0_BIT) ? " tex-0," : "",
(flags & RADEON_TEX1_BIT) ? " tex-1," : "",
+ (flags & RADEON_TEX2_BIT) ? " tex-2," : "",
(flags & RADEON_PTEX_BIT) ? " proj-tex," : "");
}
@@ -317,7 +363,10 @@
if (ctx->Fog.Enabled || (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR))
ind |= RADEON_SPEC_BIT;
- if (ctx->Texture._EnabledUnits & 0x2)
+ if (ctx->Texture._EnabledUnits & 0x4)
+ /* unit 2 enabled */
+ ind |= RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_TEX2_BIT;
+ else if (ctx->Texture._EnabledUnits & 0x2)
/* unit 1 enabled */
ind |= RADEON_TEX0_BIT|RADEON_TEX1_BIT;
else if (ctx->Texture._EnabledUnits & 0x1)
@@ -737,6 +786,9 @@
if (ctx->Texture.Unit[1]._ReallyEnabled)
inputs |= VERT_BIT_TEX1;
+ if (ctx->Texture.Unit[2]._ReallyEnabled)
+ inputs |= VERT_BIT_TEX2;
+
if (ctx->Fog.Enabled)
inputs |= VERT_BIT_FOG;
}
@@ -777,7 +829,7 @@
* don't do anything. (Maybe need to configure swrast to match hw)
*/
struct texrect_stage_data {
- GLvector4f texcoord[MAX_TEXTURE_UNITS];
+ GLvector4f texcoord[MAX_TEXTURE_UNITS]; /* question: this is mesas max-units, didn't you want RADEON_MAX_TEXTURE_UNITS ? */
};
#define TEXRECT_STAGE_DATA(stage) ((struct texrect_stage_data *)stage->privatePtr)
@@ -858,6 +910,9 @@
if (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT)
flags |= VERT_BIT_TEX1;
+ if (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT)
+ flags |= VERT_BIT_TEX2;
+
stage->inputs = flags;
stage->outputs = flags;
stage->active = (flags != 0);
@@ -870,7 +925,7 @@
GLuint i;
if (store) {
- for (i = 0 ; i < MAX_TEXTURE_UNITS ; i++)
+ for (i = 0 ; i < MAX_TEXTURE_UNITS ; i++) /* question: this is mesas max-units, didn't you want RADEON_MAX_TEXTURE_UNITS ? */
if (store->texcoord[i].data)
_mesa_vector4f_free( &store->texcoord[i] );
FREE( store );
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_tcl.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_tcl.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_tcl.c Fri May 2 13:01:54 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_tcl.c Thu Jun 19 14:02:42 2003
@@ -385,6 +385,16 @@
}
}
+ if (ctx->Texture.Unit[2]._ReallyEnabled) {
+ if (ctx->Texture.Unit[2].TexGenEnabled) {
+ if (rmesa->TexGenNeedNormals[2]) {
+ inputs |= VERT_BIT_NORMAL;
+ }
+ } else {
+ inputs |= VERT_BIT_TEX2;
+ }
+ }
+
stage->inputs = inputs;
stage->active = 1;
}
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c Wed Jun 11 00:06:20 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c Fri Jun 20 22:29:21 2003
@@ -1619,7 +1619,8 @@
GLboolean ok;
ok = (radeonUpdateTextureUnit( ctx, 0 ) &&
- radeonUpdateTextureUnit( ctx, 1 ));
+ radeonUpdateTextureUnit( ctx, 1 ) &&
+ radeonUpdateTextureUnit( ctx, 2 ));
FALLBACK( rmesa, RADEON_FALLBACK_TEXTURE, !ok );
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt.c Fri May 2 13:01:56 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt.c Sat Jun 21 10:14:22 2003
@@ -146,6 +146,13 @@
ctx->Current.Attrib[VERT_ATTRIB_TEX1][3] = 1.0F;
}
+ if (rmesa->vb.vertex_format & RADEON_CP_VC_FRMT_ST2) {
+ ctx->Current.Attrib[VERT_ATTRIB_TEX2][0] = rmesa->vb.texcoordptr[2][0];
+ ctx->Current.Attrib[VERT_ATTRIB_TEX2][1] = rmesa->vb.texcoordptr[2][1];
+ ctx->Current.Attrib[VERT_ATTRIB_TEX2][2] = 0.0F;
+ ctx->Current.Attrib[VERT_ATTRIB_TEX2][3] = 1.0F;
+ }
+
ctx->Driver.NeedFlush &= ~FLUSH_UPDATE_CURRENT;
}
@@ -262,7 +269,7 @@
* memory. Could also use the counter/notify mechanism to populate
* tmp on the fly as vertices are generated.
*/
-static GLuint copy_dma_verts( radeonContextPtr rmesa, GLfloat (*tmp)[15] )
+static GLuint copy_dma_verts( radeonContextPtr rmesa, GLfloat (*tmp)[RADEON_MAX_VERTEX_SIZE] ) /* question: is this change necessary? */
{
GLuint ovf, i;
GLuint nr = (rmesa->vb.initial_counter - rmesa->vb.counter) - rmesa->vb.primlist[rmesa->vb.nrprims].start;
@@ -354,7 +361,7 @@
{
GET_CURRENT_CONTEXT(ctx);
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat tmp[3][15];
+ GLfloat tmp[3][RADEON_MAX_VERTEX_SIZE];
GLuint i, prim;
GLuint ind = rmesa->vb.vertex_format;
GLuint nrverts;
@@ -430,6 +437,11 @@
glMultiTexCoord2fvARB( GL_TEXTURE1_ARB, &tmp[i][offset] );
offset += 2;
}
+
+ if (ind & RADEON_CP_VC_FRMT_ST2) {
+ glMultiTexCoord2fvARB( GL_TEXTURE2_ARB, &tmp[i][offset] );
+ offset += 2;
+ }
glVertex3fv( &tmp[i][0] );
}
@@ -460,6 +472,9 @@
if (ind & RADEON_CP_VC_FRMT_ST1)
glMultiTexCoord2fvARB( GL_TEXTURE1_ARB, rmesa->vb.texcoordptr[1] );
+
+ if (ind & RADEON_CP_VC_FRMT_ST2)
+ glMultiTexCoord2fvARB( GL_TEXTURE2_ARB, rmesa->vb.texcoordptr[2] );
}
@@ -468,7 +483,7 @@
{
GET_CURRENT_CONTEXT(ctx);
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat tmp[3][15];
+ GLfloat tmp[3][RADEON_MAX_VERTEX_SIZE];
GLuint i, nrverts;
if (RADEON_DEBUG & (DEBUG_VFMT|DEBUG_PRIMS))
@@ -611,6 +626,22 @@
}
}
+ if (ctx->Texture.Unit[2]._ReallyEnabled) {
+ if (ctx->Texture.Unit[2].TexGenEnabled) {
+ if (rmesa->TexGenNeedNormals[2]) {
+ ind |= RADEON_CP_VC_FRMT_N0;
+ }
+ } else {
+ if (ctx->Current.Attrib[VERT_ATTRIB_TEX2][2] != 0.0F ||
+ ctx->Current.Attrib[VERT_ATTRIB_TEX2][3] != 1.0) {
+ if (RADEON_DEBUG & (DEBUG_VFMT|DEBUG_FALLBACKS))
+ fprintf(stderr, "%s: rq2\n", __FUNCTION__);
+ return GL_FALSE;
+ }
+ ind |= RADEON_CP_VC_FRMT_ST2;
+ }
+ }
+
if (RADEON_DEBUG & (DEBUG_VFMT|DEBUG_STATE))
fprintf(stderr, "%s: format: 0x%x\n", __FUNCTION__, ind );
@@ -626,6 +657,7 @@
rmesa->vb.floatspecptr = ctx->Current.Attrib[VERT_ATTRIB_COLOR1];
rmesa->vb.texcoordptr[0] = ctx->Current.Attrib[VERT_ATTRIB_TEX0];
rmesa->vb.texcoordptr[1] = ctx->Current.Attrib[VERT_ATTRIB_TEX1];
+ rmesa->vb.texcoordptr[2] = ctx->Current.Attrib[VERT_ATTRIB_TEX2];
/* Run through and initialize the vertex components in the order
* the hardware understands:
@@ -683,6 +715,13 @@
rmesa->vb.texcoordptr[1][1] = ctx->Current.Attrib[VERT_ATTRIB_TEX1][1];
}
+ if (ind & RADEON_CP_VC_FRMT_ST2) {
+ rmesa->vb.texcoordptr[2] = &rmesa->vb.vertex[rmesa->vb.vertex_size].f;
+ rmesa->vb.vertex_size += 2;
+ rmesa->vb.texcoordptr[2][0] = ctx->Current.Attrib[VERT_ATTRIB_TEX2][0];
+ rmesa->vb.texcoordptr[2][1] = ctx->Current.Attrib[VERT_ATTRIB_TEX2][1];
+ }
+
if (rmesa->vb.installed_vertex_format != rmesa->vb.vertex_format) {
if (RADEON_DEBUG & DEBUG_VFMT)
fprintf(stderr, "reinstall on vertex_format change\n");
@@ -691,7 +730,10 @@
}
if (RADEON_DEBUG & DEBUG_VFMT)
+ {
+ fprintf(stderr, "%s rmesa->vb.vertex_size=%d\n", __FUNCTION__, rmesa->vb.vertex_size);
fprintf(stderr, "%s -- success\n", __FUNCTION__);
+ }
return GL_TRUE;
}
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_c.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_c.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_c.c Fri May 2 13:01:56 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_c.c Thu Jun 19 14:02:42 2003
@@ -548,12 +548,15 @@
* with 0x1F. Masking with 0x1F and then masking with 0x01 is redundant, so
* the subtraction has been omitted.
*/
+/* question: should we continue using this and make the texcoordptr 4 elements
+ * or should we mask and verify that the index doesn't get bigger than 2 ?
+ */
static void radeon_MultiTexCoord1fARB( GLenum target, GLfloat s )
{
GET_CURRENT_CONTEXT(ctx);
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.texcoordptr[target & 1];
+ GLfloat *dest = rmesa->vb.texcoordptr[target & 3];
dest[0] = s;
dest[1] = 0;
}
@@ -562,7 +565,7 @@
{
GET_CURRENT_CONTEXT(ctx);
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.texcoordptr[target & 1];
+ GLfloat *dest = rmesa->vb.texcoordptr[target & 3];
dest[0] = v[0];
dest[1] = 0;
}
@@ -571,7 +574,7 @@
{
GET_CURRENT_CONTEXT(ctx);
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.texcoordptr[target & 1];
+ GLfloat *dest = rmesa->vb.texcoordptr[target & 3];
dest[0] = s;
dest[1] = t;
}
@@ -580,7 +583,7 @@
{
GET_CURRENT_CONTEXT(ctx);
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.texcoordptr[target & 1];
+ GLfloat *dest = rmesa->vb.texcoordptr[target & 3];
dest[0] = v[0];
dest[1] = v[1];
}
@@ -736,17 +739,20 @@
#define ACTIVE_ST0 RADEON_CP_VC_FRMT_ST0
#define ACTIVE_ST1 RADEON_CP_VC_FRMT_ST1
-#define ACTIVE_ST_ALL (RADEON_CP_VC_FRMT_ST1|RADEON_CP_VC_FRMT_ST0)
+#define ACTIVE_ST2 RADEON_CP_VC_FRMT_ST2
+#define ACTIVE_ST_ALL (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1|RADEON_CP_VC_FRMT_ST2)
/* Each codegen function should be able to be fully specified by a
* subsetted version of rmesa->vb.vertex_format.
*/
+ /* question: this is strange... could someone explain ? */
#define MASK_NORM (ACTIVE_XYZW)
#define MASK_COLOR (MASK_NORM|ACTIVE_NORM)
#define MASK_SPEC (MASK_COLOR|ACTIVE_COLOR)
#define MASK_ST0 (MASK_SPEC|ACTIVE_SPEC)
#define MASK_ST1 (MASK_ST0|ACTIVE_ST0)
-#define MASK_ST_ALL (MASK_ST1|ACTIVE_ST1)
+#define MASK_ST2 (MASK_ST1|ACTIVE_ST1)
+#define MASK_ST_ALL (MASK_ST2|ACTIVE_ST2)
#define MASK_VERTEX (MASK_ST_ALL|ACTIVE_FPALPHA)
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_sse.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_sse.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_sse.c Fri May 2 13:01:56 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_sse.c Thu Jun 19 14:02:42 2003
@@ -178,10 +178,10 @@
if (RADEON_DEBUG & DEBUG_CODEGEN)
fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
- if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) ==
+ if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) == /* FIXME: what should we do here ? */
(RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) {
DFN ( _sse_MultiTexCoord2fv, rmesa->vb.dfn_cache.MultiTexCoord2fvARB );
- FIXUP(dfn->code, 18, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]);
+ FIXUP(dfn->code, 18, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]); /* FIXME: whats that ? */
} else {
DFN ( _sse_MultiTexCoord2fv_2, rmesa->vb.dfn_cache.MultiTexCoord2fvARB );
FIXUP(dfn->code, 14, 0x0, (int)rmesa->vb.texcoordptr);
@@ -197,7 +197,7 @@
if (RADEON_DEBUG & DEBUG_CODEGEN)
fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
- if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) ==
+ if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) == /* FIXME: and here? */
(RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) {
DFN ( _sse_MultiTexCoord2f, rmesa->vb.dfn_cache.MultiTexCoord2fARB );
FIXUP(dfn->code, 16, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]);
diff -ru current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_x86.c tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_x86.c
--- current_trunk/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_x86.c Fri May 2 13:01:56 2003
+++ tex3_20030619/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_x86.c Thu Jun 19 14:02:42 2003
@@ -75,7 +75,7 @@
if (RADEON_DEBUG & DEBUG_CODEGEN)
fprintf(stderr, "%s 0x%08x %d\n", __FUNCTION__, key, rmesa->vb.vertex_size );
- switch (rmesa->vb.vertex_size) {
+ switch (rmesa->vb.vertex_size) { /* FIXME: do we need something here? */
case 4: {
DFN ( _x86_Vertex3f_4, rmesa->vb.dfn_cache.Vertex3f );
@@ -127,7 +127,7 @@
if (RADEON_DEBUG & DEBUG_CODEGEN)
fprintf(stderr, "%s 0x%08x %d\n", __FUNCTION__, key, rmesa->vb.vertex_size );
- switch (rmesa->vb.vertex_size) {
+ switch (rmesa->vb.vertex_size) { /* FIXME: and here */
case 6: {
DFN ( _x86_Vertex3fv_6, rmesa->vb.dfn_cache.Vertex3fv );
@@ -359,7 +359,7 @@
if (RADEON_DEBUG & DEBUG_CODEGEN)
fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
- if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) ==
+ if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) == /* FIXME: what should be done here? */
(RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) {
DFN ( _x86_MultiTexCoord2fv, rmesa->vb.dfn_cache.MultiTexCoord2fvARB );
FIXUP(dfn->code, 21, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]);
@@ -380,7 +380,7 @@
if (RADEON_DEBUG & DEBUG_CODEGEN)
fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
- if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) ==
+ if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) == /* FIXME: and here */
(RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) {
DFN ( _x86_MultiTexCoord2f, rmesa->vb.dfn_cache.MultiTexCoord2fARB );
FIXUP(dfn->code, 20, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]);
diff -ru current_trunk/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h tex3_20030619/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h
--- current_trunk/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h Wed Jun 11 00:10:48 2003
+++ tex3_20030619/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h Thu Jun 19 14:02:42 2003
@@ -357,7 +357,13 @@
#define RADEON_EMIT_PP_TEX_SIZE_0 73
#define RADEON_EMIT_PP_TEX_SIZE_1 74
#define RADEON_EMIT_PP_TEX_SIZE_2 75
-#define RADEON_MAX_STATE_PACKETS 76
+#define RADEON_EMIT_PP_CUBIC_FACES_0 76
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 77
+#define RADEON_EMIT_PP_CUBIC_FACES_1 78
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 79
+#define RADEON_EMIT_PP_CUBIC_FACES_2 80
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 81
+#define RADEON_MAX_STATE_PACKETS 82
/* Commands understood by cmd_buffer ioctl. More can be added but
diff -ru current_trunk/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h tex3_20030619/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h
--- current_trunk/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h Wed Jun 11 00:10:49 2003
+++ tex3_20030619/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h Thu Jun 19 14:02:42 2003
@@ -1197,9 +1197,10 @@
# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20
# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
-# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
+# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
+# define RADEON_TXFORMAT_ST_ROUTE_SHIFT 24
# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)
# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)
# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)
diff -ru current_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon.h tex3_20030619/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon.h
--- current_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon.h Wed Jun 11 00:14:43 2003
+++ tex3_20030619/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon.h Fri Jun 20 23:03:54 2003
@@ -80,6 +80,11 @@
* 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
* Add 'GET' queries for starting additional clients on different VT's.
* Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
+ * 1.9 - Add support for NPOT Texture registers on radeon:
+ * RADEON_PP_TEX_SIZE_[0..2] (RADEON_EMIT_PP_TEX_SIZE_[0..2])
+ * Add support for cube map registers on radeon:
+ * RADEON_PP_CUBIC_FACES_[0..2] (RADEON_EMIT_CUBIC_FACES_[0..2])
+ * RADEON_PP_CUBIC_OFFSET_T[0..2]_0 (RADEON_EMIT_CUBIC_OFFSETS_T[0..2])
*/
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \
diff -ru current_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h tex3_20030619/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h
--- current_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h Wed Jun 11 00:14:44 2003
+++ tex3_20030619/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h Thu Jun 19 14:02:42 2003
@@ -144,7 +144,13 @@
#define RADEON_EMIT_PP_TEX_SIZE_0 73
#define RADEON_EMIT_PP_TEX_SIZE_1 74
#define RADEON_EMIT_PP_TEX_SIZE_2 75
-#define RADEON_MAX_STATE_PACKETS 76
+#define RADEON_EMIT_PP_CUBIC_FACES_0 76
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 77
+#define RADEON_EMIT_PP_CUBIC_FACES_1 78
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 79
+#define RADEON_EMIT_PP_CUBIC_FACES_2 80
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 81
+#define RADEON_MAX_STATE_PACKETS 82
/* Commands understood by cmd_buffer ioctl. More can be added but
diff -ru current_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h tex3_20030619/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h
--- current_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h Wed Jun 11 00:14:44 2003
+++ tex3_20030619/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h Thu Jun 19 14:02:42 2003
@@ -673,6 +673,12 @@
#define RADEON_PP_TEX_SIZE_1 0x1d0c
#define RADEON_PP_TEX_SIZE_2 0x1d14
+#define RADEON_PP_CUBIC_FACES_0 0x1d24
+#define RADEON_PP_CUBIC_FACES_1 0x1d28
+#define RADEON_PP_CUBIC_FACES_2 0x1d2c
+#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
+#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
+#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
diff -ru current_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c tex3_20030619/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c
--- current_trunk/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c Thu Jun 19 12:37:35 2003
+++ tex3_20030619/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c Thu Jun 19 14:02:42 2003
@@ -295,6 +295,12 @@
{ RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
+ { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" },
+ { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
+ { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" },
+ { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
+ { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
+ { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
};
