Hi,
The attached patches enable HyperZ on radeon (RV100 only for now).
People always ask me for an HyperZ benchmark, so :
HyperZ gets me 45% more fps (48 fps -> 70 fps) in Quake3 four.dm68 (Radeon 7000, athlon XP 2600).
It also speeds up glxgears from 450 fps to 1300 fps, which shows how useless glxears is as a benchmark :)
My case is probably a bit extreme though, since my video card is slow compared to my CPU.
The patch needs some more work for non-RV100 radeon cards, but the basics are here.
For the R200, I attached a patch-over-the-patch done by Jacek Poplawski which doesn't work yet (but doesn't crash, at least).
This patch will probably help to get started with an R100 version too (although the R100 doesn't need the RADEON_3D_CLEAR_HIZ thing)
Big thanks to the people who helped me with this, especially Eric Anholt and the nice people on irc :)
Stephane
Index: src/mesa/drivers/dri/common/xmlpool.h
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/common/xmlpool.h,v
retrieving revision 1.8
diff -u -r1.8 xmlpool.h
--- src/mesa/drivers/dri/common/xmlpool.h 7 Oct 2004 23:30:29 -0000 1.8
+++ src/mesa/drivers/dri/common/xmlpool.h 1 Nov 2004 19:52:51 -0000
@@ -273,6 +273,14 @@
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
+#define DRI_CONF_HYPERZ_DISABLED 0
+#define DRI_CONF_HYPERZ_ENABLED 1
+#define DRI_CONF_HYPERZ(def) \
+DRI_CONF_OPT_BEGIN(hyperz,bool,def) \
+ DRI_CONF_DESC(en,"Use hyperz") \
+ DRI_CONF_DESC(de,"Hyperz antreiben") \
+DRI_CONF_OPT_END
+
#define DRI_CONF_MAX_TEXTURE_UNITS(def,min,max) \
DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max ) \
DRI_CONF_DESC(en,"Number of texture units") \
Index: src/mesa/drivers/dri/r200/r200_context.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/r200/r200_context.c,v
retrieving revision 1.33
diff -u -r1.33 r200_context.c
--- src/mesa/drivers/dri/r200/r200_context.c 7 Oct 2004 23:30:30 -0000 1.33
+++ src/mesa/drivers/dri/r200/r200_context.c 1 Nov 2004 19:52:52 -0000
@@ -262,6 +262,14 @@
rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
"def_max_anisotropy");
+ if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
+ if ( sPriv->drmMinor < 13 )
+ fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
+ "disabling.\n",sPriv->drmMinor );
+ else
+ rmesa->using_hyperz = GL_TRUE;
+ }
+
/* Init default driver functions then plug in our R200-specific functions
* (the texture functions are especially important)
*/
Index: src/mesa/drivers/dri/r200/r200_context.h
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/r200/r200_context.h,v
retrieving revision 1.23
diff -u -r1.23 r200_context.h
--- src/mesa/drivers/dri/r200/r200_context.h 16 Oct 2004 03:36:14 -0000 1.23
+++ src/mesa/drivers/dri/r200/r200_context.h 1 Nov 2004 19:52:53 -0000
@@ -925,6 +925,8 @@
/* Configuration cache
*/
driOptionCache optionCache;
+
+ GLboolean using_hyperz;
};
#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx))
Index: src/mesa/drivers/dri/r200/r200_ioctl.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/r200/r200_ioctl.c,v
retrieving revision 1.22
diff -u -r1.22 r200_ioctl.c
--- src/mesa/drivers/dri/r200/r200_ioctl.c 2 Oct 2004 05:22:19 -0000 1.22
+++ src/mesa/drivers/dri/r200/r200_ioctl.c 1 Nov 2004 19:52:53 -0000
@@ -610,7 +610,10 @@
}
if ( mask & DD_DEPTH_BIT ) {
- if ( ctx->Depth.Mask ) flags |= RADEON_DEPTH; /* FIXME: ??? */
+ if ( ctx->Depth.Mask ) {
+ flags |= RADEON_DEPTH; /* FIXME: ??? */
+ if (rmesa->using_hyperz) flags |= RADEON_CLEAR_HYPERZ;
+ }
mask &= ~DD_DEPTH_BIT;
}
Index: src/mesa/drivers/dri/r200/r200_screen.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/r200/r200_screen.c,v
retrieving revision 1.29
diff -u -r1.29 r200_screen.c
--- src/mesa/drivers/dri/r200/r200_screen.c 7 Oct 2004 23:30:30 -0000 1.29
+++ src/mesa/drivers/dri/r200/r200_screen.c 1 Nov 2004 19:52:53 -0000
@@ -63,6 +63,7 @@
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
DRI_CONF_MAX_TEXTURE_UNITS(4,2,6)
+ DRI_CONF_HYPERZ(true)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
@@ -81,7 +82,7 @@
DRI_CONF_NV_VERTEX_PROGRAM(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
-static const GLuint __driNConfigOptions = 14;
+static const GLuint __driNConfigOptions = 15;
#if 1
/* Including xf86PciInfo.h introduces a bunch of errors...
Index: src/mesa/drivers/dri/r200/r200_state_init.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/r200/r200_state_init.c,v
retrieving revision 1.17
diff -u -r1.17 r200_state_init.c
--- src/mesa/drivers/dri/r200/r200_state_init.c 16 Oct 2004 03:36:14 -0000 1.17
+++ src/mesa/drivers/dri/r200/r200_state_init.c 1 Nov 2004 19:52:54 -0000
@@ -51,6 +51,7 @@
#include "r200_tex.h"
#include "r200_swtcl.h"
#include "r200_vtxfmt.h"
+#include "radeon_reg.h"
#include "xmlpool.h"
@@ -447,7 +448,8 @@
rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
((rmesa->r200Screen->depthPitch &
R200_DEPTHPITCH_MASK) |
- R200_DEPTH_ENDIAN_NO_SWAP);
+ RADEON_DEPTH_ENDIAN_NO_SWAP |
+ RADEON_DEPTH_HYPERZ);
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
R200_Z_TEST_LESS |
@@ -457,6 +459,11 @@
R200_STENCIL_ZFAIL_KEEP |
R200_Z_WRITE_ENABLE);
+ if (rmesa->using_hyperz)
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE |
+ RADEON_Z_COMPRESSION_ENABLE |
+ RADEON_Z_DECOMPRESSION_ENABLE;
+
rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
| R200_TEX_BLEND_0_ENABLE);
Index: src/mesa/drivers/dri/radeon/radeon_context.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_context.c,v
retrieving revision 1.25
diff -u -r1.25 radeon_context.c
--- src/mesa/drivers/dri/radeon/radeon_context.c 7 Oct 2004 23:30:30 -0000
1.25
+++ src/mesa/drivers/dri/radeon/radeon_context.c 1 Nov 2004 19:52:55 -0000
@@ -245,6 +245,14 @@
rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
"def_max_anisotropy");
+ if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
+ if ( sPriv->drmMinor < 13 )
+ fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
+ "disabling.\n",sPriv->drmMinor );
+ else
+ rmesa->using_hyperz = GL_TRUE;
+ }
+
/* Init default driver functions then plug in our Radeon-specific functions
* (the texture functions are especially important)
*/
Index: src/mesa/drivers/dri/radeon/radeon_context.h
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_context.h,v
retrieving revision 1.17
diff -u -r1.17 radeon_context.h
--- src/mesa/drivers/dri/radeon/radeon_context.h 30 Sep 2004 00:08:05 -0000
1.17
+++ src/mesa/drivers/dri/radeon/radeon_context.h 1 Nov 2004 19:52:55 -0000
@@ -783,6 +783,8 @@
driOptionCache optionCache;
+ GLboolean using_hyperz;
+
/* Performance counters
*/
GLuint boxes; /* Draw performance boxes */
Index: src/mesa/drivers/dri/radeon/radeon_ioctl.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_ioctl.c,v
retrieving revision 1.15
diff -u -r1.15 radeon_ioctl.c
--- src/mesa/drivers/dri/radeon/radeon_ioctl.c 30 Sep 2004 00:08:05 -0000 1.15
+++ src/mesa/drivers/dri/radeon/radeon_ioctl.c 1 Nov 2004 19:52:56 -0000
@@ -1031,7 +1031,10 @@
}
if ( mask & DD_DEPTH_BIT ) {
- if ( ctx->Depth.Mask ) flags |= RADEON_DEPTH; /* FIXME: ??? */
+ if ( ctx->Depth.Mask ) {
+ flags |= RADEON_DEPTH; /* FIXME: ??? */
+ if (rmesa->using_hyperz) flags |= RADEON_CLEAR_HYPERZ;
+ }
mask &= ~DD_DEPTH_BIT;
}
Index: src/mesa/drivers/dri/radeon/radeon_screen.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c,v
retrieving revision 1.21
diff -u -r1.21 radeon_screen.c
--- src/mesa/drivers/dri/radeon/radeon_screen.c 7 Oct 2004 23:30:30 -0000 1.21
+++ src/mesa/drivers/dri/radeon/radeon_screen.c 1 Nov 2004 19:52:56 -0000
@@ -60,6 +60,7 @@
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
+ DRI_CONF_HYPERZ(true)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
@@ -74,7 +75,7 @@
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
-static const GLuint __driNConfigOptions = 11;
+static const GLuint __driNConfigOptions = 12;
#if 1
/* Including xf86PciInfo.h introduces a bunch of errors...
Index: src/mesa/drivers/dri/radeon/radeon_state_init.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_state_init.c,v
retrieving revision 1.10
diff -u -r1.10 radeon_state_init.c
--- src/mesa/drivers/dri/radeon/radeon_state_init.c 30 Sep 2004 00:08:05 -0000
1.10
+++ src/mesa/drivers/dri/radeon/radeon_state_init.c 1 Nov 2004 19:52:56 -0000
@@ -45,6 +45,7 @@
#include "radeon_tex.h"
#include "radeon_swtcl.h"
#include "radeon_vtxfmt.h"
+#include "radeon_reg.h"
#include "xmlpool.h"
@@ -328,7 +329,8 @@
rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
((rmesa->radeonScreen->depthPitch &
RADEON_DEPTHPITCH_MASK) |
- RADEON_DEPTH_ENDIAN_NO_SWAP);
+ RADEON_DEPTH_ENDIAN_NO_SWAP |
+ RADEON_DEPTH_HYPERZ);
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
RADEON_Z_TEST_LESS |
@@ -338,6 +340,11 @@
RADEON_STENCIL_ZFAIL_KEEP |
RADEON_Z_WRITE_ENABLE);
+ if (rmesa->using_hyperz)
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE |
+ RADEON_Z_COMPRESSION_ENABLE |
+ RADEON_Z_DECOMPRESSION_ENABLE;
+
rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
RADEON_ANTI_ALIAS_NONE);
Index: src/mesa/drivers/dri/radeon/server/radeon_reg.h
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/server/radeon_reg.h,v
retrieving revision 1.4
diff -u -r1.4 radeon_reg.h
--- src/mesa/drivers/dri/radeon/server/radeon_reg.h 21 Oct 2003 06:05:51 -0000
1.4
+++ src/mesa/drivers/dri/radeon/server/radeon_reg.h 1 Nov 2004 19:52:59 -0000
@@ -1555,6 +1555,7 @@
# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)
# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)
# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)
+# define RADEON_DEPTH_HYPERZ (3 << 16)
#define RADEON_RB3D_PLANEMASK 0x1d84
#define RADEON_RB3D_ROPCNTL 0x1d80
# define RADEON_ROP_MASK (15 << 8)
@@ -1600,6 +1601,7 @@
# define RADEON_Z_TEST_NEQUAL (6 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
# define RADEON_Z_TEST_MASK (7 << 4)
+# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
# define RADEON_STENCIL_TEST_NEVER (0 << 12)
# define RADEON_STENCIL_TEST_LESS (1 << 12)
# define RADEON_STENCIL_TEST_LEQUAL (2 << 12)
@@ -1633,6 +1635,7 @@
# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
+# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
#define RADEON_RE_LINE_PATTERN 0x1cd0
# define RADEON_LINE_PATTERN_MASK 0x0000ffff
# define RADEON_LINE_REPEAT_COUNT_SHIFT 16
Index: shared/drm_pciids.txt
===================================================================
RCS file: /cvs/dri/drm/shared/drm_pciids.txt,v
retrieving revision 1.8
diff -u -r1.8 drm_pciids.txt
--- shared/drm_pciids.txt 22 Sep 2004 22:51:18 -0000 1.8
+++ shared/drm_pciids.txt 1 Nov 2004 18:39:39 -0000
@@ -1,24 +1,24 @@
[radeon]
-0x1002 0x4136 CHIP_RS100|CHIP_IS_IGP "ATI Radeon RS100 IGP 320M"
-0x1002 0x4137 CHIP_RS200|CHIP_IS_IGP "ATI Radeon RS200 IGP"
-0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP "ATI Radeon RS250 IGP"
+0x1002 0x4136 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS100 IGP 320M"
+0x1002 0x4137 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS200 IGP"
+0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS250 IGP"
0x1002 0x4242 CHIP_R200 "ATI Radeon BB R200 AIW 8500DV"
0x1002 0x4242 CHIP_R200 "ATI Radeon BC R200"
-0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS100 Mobility U1"
-0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS200 Mobility IGP
340M"
-0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS250 Mobility IGP"
-0x1002 0x4964 CHIP_R250 "ATI Radeon Id R250 9000"
-0x1002 0x4965 CHIP_R250 "ATI Radeon Ie R250 9000"
-0x1002 0x4966 CHIP_R250 "ATI Radeon If R250 9000"
-0x1002 0x4967 CHIP_R250 "ATI Radeon Ig R250 9000"
-0x1002 0x4C57 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LW RV200 Mobility 7500 M7"
-0x1002 0x4C58 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LX RV200 Mobility FireGL 7800
M7"
-0x1002 0x4C59 CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LY RV100 Mobility M6"
-0x1002 0x4C5A CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LZ RV100 Mobility M6"
-0x1002 0x4C64 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Ld R250 Mobility 9000 M9"
-0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Le R250 Mobility 9000 M9"
-0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lf R250 Mobility 9000 M9"
-0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lg R250 Mobility 9000 M9"
+0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RS100
Mobility U1"
+0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RS200
Mobility IGP 340M"
+0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RS250
Mobility IGP"
+0x1002 0x4964 CHIP_R250|CHIP_IS_RV "ATI Radeon Id R250 9000"
+0x1002 0x4965 CHIP_R250|CHIP_IS_RV "ATI Radeon Ie R250 9000"
+0x1002 0x4966 CHIP_R250|CHIP_IS_RV "ATI Radeon If R250 9000"
+0x1002 0x4967 CHIP_R250|CHIP_IS_RV "ATI Radeon Ig R250 9000"
+0x1002 0x4C57 CHIP_RV200|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon LW RV200 Mobility
7500 M7"
+0x1002 0x4C58 CHIP_RV200|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon LX RV200 Mobility
FireGL 7800 M7"
+0x1002 0x4C59 CHIP_RV100|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon LY RV100 Mobility M6"
+0x1002 0x4C5A CHIP_RV100|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon LZ RV100 Mobility M6"
+0x1002 0x4C64 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Ld R250 Mobility 9000
M9"
+0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Le R250 Mobility 9000
M9"
+0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Lf R250 Mobility 9000
M9"
+0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Lg R250 Mobility 9000
M9"
0x1002 0x5144 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QD R100"
0x1002 0x5145 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QE R100"
0x1002 0x5146 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QF R100"
@@ -31,10 +31,10 @@
0x1002 0x514D CHIP_R200 "ATI Radeon QM R200 9100"
0x1002 0x514E CHIP_R200 "ATI Radeon QN R200 8500 LE"
0x1002 0x514F CHIP_R200 "ATI Radeon QO R200 8500 LE"
-0x1002 0x5157 CHIP_RV200 "ATI Radeon QW RV200 7500"
-0x1002 0x5158 CHIP_RV200 "ATI Radeon QX RV200 7500"
-0x1002 0x5159 CHIP_RV100 "ATI Radeon QY RV100 7000/VE"
-0x1002 0x515A CHIP_RV100 "ATI Radeon QZ RV100 7000/VE"
+0x1002 0x5157 CHIP_RV200|CHIP_IS_RV "ATI Radeon QW RV200 7500"
+0x1002 0x5158 CHIP_RV200|CHIP_IS_RV "ATI Radeon QX RV200 7500"
+0x1002 0x5159 CHIP_RV100|CHIP_IS_RV "ATI Radeon QY RV100 7000/VE"
+0x1002 0x515A CHIP_RV100|CHIP_IS_RV "ATI Radeon QZ RV100 7000/VE"
0x1002 0x5168 CHIP_R200 "ATI Radeon Qh R200"
0x1002 0x5169 CHIP_R200 "ATI Radeon Qi R200"
0x1002 0x516A CHIP_R200 "ATI Radeon Qj R200"
@@ -44,19 +44,19 @@
0x1002 0x5835 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS300 Mobility IGP"
0x1002 0x5836 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
0x1002 0x5837 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200 SE"
-0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5963 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5964 CHIP_RV280 "ATI Radeon RV280 9200 SE"
-0x1002 0x5968 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5969 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x596A CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x596B CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5c61 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility"
-0x1002 0x5c62 CHIP_RV280 "ATI Radeon RV280"
-0x1002 0x5c63 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility"
-0x1002 0x5c64 CHIP_RV280 "ATI Radeon RV280"
+0x1002 0x5960 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5961 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200 SE"
+0x1002 0x5962 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5963 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5964 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200 SE"
+0x1002 0x5968 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5969 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x596A CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x596B CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5c61 CHIP_RV280|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV280 Mobility"
+0x1002 0x5c62 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280"
+0x1002 0x5c63 CHIP_RV280|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV280 Mobility"
+0x1002 0x5c64 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280"
[r128]
0x1002 0x4c45 0 "ATI Rage 128 Mobility LE (PCI)"
Index: shared/radeon.h
===================================================================
RCS file: /cvs/dri/drm/shared/radeon.h,v
retrieving revision 1.33
diff -u -r1.33 radeon.h
--- shared/radeon.h 23 Oct 2004 06:25:56 -0000 1.33
+++ shared/radeon.h 1 Nov 2004 18:39:40 -0000
@@ -45,7 +45,7 @@
#define DRIVER_DATE "20020828"
#define DRIVER_MAJOR 1
-#define DRIVER_MINOR 12
+#define DRIVER_MINOR 13
#define DRIVER_PATCHLEVEL 0
/* Interface history:
@@ -82,6 +82,7 @@
* and GL_EXT_blend_[func|equation]_separate on r200
* 1.12- Add R300 CP microcode support - this just loads the CP on r300
* (No 3D support yet - just microcode loading).
+ * 1.13- Added RADEON_CLEAR_HYPERZ flag to clear ioctl.
*/
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \
Index: shared/radeon_drm.h
===================================================================
RCS file: /cvs/dri/drm/shared/radeon_drm.h,v
retrieving revision 1.24
diff -u -r1.24 radeon_drm.h
--- shared/radeon_drm.h 23 Oct 2004 06:25:56 -0000 1.24
+++ shared/radeon_drm.h 1 Nov 2004 18:39:40 -0000
@@ -193,6 +193,7 @@
#define RADEON_BACK 0x2
#define RADEON_DEPTH 0x4
#define RADEON_STENCIL 0x8
+#define RADEON_CLEAR_HYPERZ 0x8000000
/* Primitive types
*/
Index: shared/radeon_drv.h
===================================================================
RCS file: /cvs/dri/drm/shared/radeon_drv.h,v
retrieving revision 1.36
diff -u -r1.36 radeon_drv.h
--- shared/radeon_drv.h 23 Oct 2004 06:25:56 -0000 1.36
+++ shared/radeon_drv.h 1 Nov 2004 18:39:41 -0000
@@ -67,6 +67,7 @@
CHIP_IS_IGP = 0x00020000UL,
CHIP_SINGLE_CRTC = 0x00040000UL,
CHIP_IS_AGP = 0x00080000UL,
+ CHIP_IS_RV = 0x00100000UL,
};
#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
@@ -410,6 +411,7 @@
# define RADEON_STENCIL_ENABLE (1 << 7)
# define RADEON_Z_ENABLE (1 << 8)
#define RADEON_RB3D_DEPTHOFFSET 0x1c24
+#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
#define RADEON_RB3D_DEPTHPITCH 0x1c28
#define RADEON_RB3D_PLANEMASK 0x1d84
#define RADEON_RB3D_STENCILREFMASK 0x1d7c
@@ -422,11 +424,15 @@
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
+# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
+# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
+# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
+# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
@@ -534,7 +540,7 @@
# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
-#define RADEON_RB3D_ZMASKOFFSET 0x1c34
+#define RADEON_RB3D_ZMASKOFFSET 0x3234
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
@@ -589,6 +595,8 @@
# define RADEON_3D_DRAW_IMMD 0x00002900
# define RADEON_3D_DRAW_INDX 0x00002A00
# define RADEON_3D_LOAD_VBPNTR 0x00002F00
+# define RADEON_3D_CLEAR_ZMASK 0x00003200
+# define RADEON_3D_CLEAR_HIZ 0x00003700
# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
# define RADEON_CNTL_PAINT_MULTI 0x00009A00
# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
Index: shared/radeon_state.c
===================================================================
RCS file: /cvs/dri/drm/shared/radeon_state.c,v
retrieving revision 1.39
diff -u -r1.39 radeon_state.c
--- shared/radeon_state.c 23 Oct 2004 06:25:56 -0000 1.39
+++ shared/radeon_state.c 1 Nov 2004 18:39:42 -0000
@@ -780,6 +780,101 @@
}
}
+ if (( flags & (RADEON_DEPTH|RADEON_STENCIL) )&&(flags & RADEON_CLEAR_HYPERZ)) {
+ /* hyper-z clear */
+ rb3d_cntl = depth_clear->rb3d_cntl;
+
+ /*
+ * Stencil buffer specific enables
+ */
+ if ( flags & RADEON_STENCIL ) {
+ rb3d_cntl |= RADEON_STENCIL_ENABLE;
+ rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
+ } else {
+ rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
+ rb3d_stencilrefmask = 0x00000000;
+ }
+
+ if ( flags & RADEON_DEPTH ) {
+ rb3d_cntl |= RADEON_Z_ENABLE;
+ } else {
+ rb3d_cntl &= ~RADEON_Z_ENABLE;
+ }
+
+ /* Make sure we restore the 3D state next time.
+ */
+ dev_priv->sarea_priv->ctx_owner = 0;
+
+ BEGIN_RING( 15 );
+ RADEON_WAIT_UNTIL_2D_IDLE();
+
+ OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
+ OUT_RING( 0x00000000 );
+ OUT_RING( rb3d_cntl );
+
+ OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
+ depth_clear->rb3d_zstencilcntl |
+ RADEON_Z_HIERARCHY_ENABLE |
+ RADEON_Z_COMPRESSION_ENABLE |
+ RADEON_Z_DECOMPRESSION_ENABLE);
+ OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
+ rb3d_stencilrefmask );
+ OUT_RING_REG( RADEON_RB3D_PLANEMASK,
+ 0x00000000 );
+ OUT_RING_REG( RADEON_SE_CNTL,
+ depth_clear->se_cntl );
+ OUT_RING_REG( RADEON_RB3D_DEPTHOFFSET,
+ dev_priv->sarea_priv->context_state.rb3d_depthoffset);
+ ADVANCE_RING();
+
+ BEGIN_RING( 8 );
+ OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE,
+ clear->clear_depth);
+ OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET,
+ 0x00000000);
+/* OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL);
+ OUT_RING( CP_PACKET3( RADEON_WAIT_FOR_IDLE, 0 ) );
+ OUT_RING( 0x11111111 );*/
+ OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) );
+ if (dev_priv->flags&CHIP_IS_RV)
+ {
+ /* clear mask : chooses the clearing pattern */
+ OUT_RING( 0x00000000 );
+ } else {
+ /* FIXME : reverse engineer that for Rx00 cards */
+ OUT_RING( 0x00000000 );
+ }
+ /* the number of tiles to clear */
+
OUT_RING(((dev_priv->depth_pitch)/(dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z?(2*16):(4*16)))*((pbox[0].y2+0xf)>>4)
);
+ if (dev_priv->flags&CHIP_IS_RV)
+ {
+ /* clear mask : chooses the clearing pattern */
+ OUT_RING( 0x00000000 );
+ } else {
+ /* FIXME : reverse engineer that for Rx00 cards */
+ OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
+ }
+ ADVANCE_RING();
+
+ if ( dev_priv->microcode_version==UCODE_R200 ) {
+ if (dev_priv->flags&CHIP_IS_RV)
+ {
+ BEGIN_RING( 4 );
+ OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) );
+ OUT_RING( 0x0 ); /* First tile */
+ OUT_RING( 0x3cc0 );
+ OUT_RING( 0x00000000 );
+ ADVANCE_RING();
+ } else {
+ BEGIN_RING( 4 );
+ OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) );
+ OUT_RING( 0x0 ); /* First tile */
+ OUT_RING( 0x3cc0 );
+ OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
+ ADVANCE_RING();
+ }
+ }
+ }
/* We have to clear the depth and/or stencil buffers by
* rendering a quad into just those buffers. Thus, we have to
* make sure the 3D engine is configured correctly.
--- radeon_state.c 2004-11-01 19:06:54.000000000 +0100
+++ /home/steph/radeon_state.c 2004-11-02 01:36:32.000000000 +0100
@@ -805,28 +805,36 @@
*/
dev_priv->sarea_priv->ctx_owner = 0;
- BEGIN_RING( 15 );
+ BEGIN_RING( 10 );
RADEON_WAIT_UNTIL_2D_IDLE();
- OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
+/* OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
OUT_RING( 0x00000000 );
- OUT_RING( rb3d_cntl );
+ OUT_RING( rb3d_cntl );*/
OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
depth_clear->rb3d_zstencilcntl |
RADEON_Z_HIERARCHY_ENABLE |
RADEON_Z_COMPRESSION_ENABLE |
RADEON_Z_DECOMPRESSION_ENABLE);
+
+ // (jp) these 3 OUT_RING_REGs changes nothing
OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
rb3d_stencilrefmask );
OUT_RING_REG( RADEON_RB3D_PLANEMASK,
0x00000000 );
OUT_RING_REG( RADEON_SE_CNTL,
depth_clear->se_cntl );
- OUT_RING_REG( RADEON_RB3D_DEPTHOFFSET,
- dev_priv->sarea_priv->context_state.rb3d_depthoffset);
+
+ // (jp) uncommenting it (and chaging 10 to 12) produces crash
+/* OUT_RING_REG( RADEON_RB3D_DEPTHOFFSET,
+ dev_priv->sarea_priv->context_state.rb3d_depthoffset);*/
+
ADVANCE_RING();
+ // (jp) without these 2 ring sections picture is even more
+ // fscked up (irregular rendering problems)
+
BEGIN_RING( 8 );
OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE,
clear->clear_depth);
@@ -836,44 +844,18 @@
OUT_RING( CP_PACKET3( RADEON_WAIT_FOR_IDLE, 0 ) );
OUT_RING( 0x11111111 );*/
OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) );
- if (dev_priv->flags&CHIP_IS_RV)
- {
- /* clear mask : chooses the clearing pattern */
- OUT_RING( 0x00000000 );
- } else {
- /* FIXME : reverse engineer that for Rx00 cards */
- OUT_RING( 0x00000000 );
- }
+ OUT_RING( 0x00000000 );
/* the number of tiles to clear */
OUT_RING(((dev_priv->depth_pitch)/(dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z?(2*16):(4*16)))*((pbox[0].y2+0xf)>>4)
);
- if (dev_priv->flags&CHIP_IS_RV)
- {
- /* clear mask : chooses the clearing pattern */
- OUT_RING( 0x00000000 );
- } else {
- /* FIXME : reverse engineer that for Rx00 cards */
- OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
- }
+ OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
ADVANCE_RING();
- if ( dev_priv->microcode_version==UCODE_R200 ) {
- if (dev_priv->flags&CHIP_IS_RV)
- {
- BEGIN_RING( 4 );
- OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) );
- OUT_RING( 0x0 ); /* First tile */
- OUT_RING( 0x3cc0 );
- OUT_RING( 0x00000000 );
- ADVANCE_RING();
- } else {
- BEGIN_RING( 4 );
- OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) );
- OUT_RING( 0x0 ); /* First tile */
- OUT_RING( 0x3cc0 );
- OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
- ADVANCE_RING();
- }
- }
+ BEGIN_RING( 4 );
+ OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) );
+ OUT_RING( 0x0 );
+ OUT_RING( 0x3cc0 );
+ OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
+ ADVANCE_RING();
}
/* We have to clear the depth and/or stencil buffers by
* rendering a quad into just those buffers. Thus, we have to
