I think the NCC error "vout in Cell:test_1:r_divider" in the sch box may
be indicating that your schematic has a vout wire, but it could not find
the matching one on the layout. So your layout may be missing vout or
it might be mislabel (a typographical error). To more easily determine
the cause, you would have to send the jelib file.
On 10/6/2017 9:27 PM, sujan kanti wrote:
On Friday, October 6, 2017 at 10:36:36 PM UTC+8, sujan kanti wrote:
Hello Sir,
I followed everything according to Dr. Jacob tutorial 1. At the
time of simulation i found this error.How can I repair it? please
help me.
I have attached the problem
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