Sorry, I currently don't know what is wrong with your circuit. Are you
following Hathaway's Lab 6 [1]?
If so, get the lab6.jelib (from [1]) and compare it with what you have
until you find out what is different.
[1]
http://cmosedu.com/jbaker/courses/ee421L/f13/students/hathawa6/lab6/lab6.htm
On 10/31/2017 8:41 AM, Paul Sujan Kanti wrote:
Thanks Sir
It is working
I am dong layout of this circuit. this is full adder circuit. I dont
have any DRC & ERC error
but I am unable to get the plot for Full adder Sum. i need you help Sir.
Here is my file
--
You received this message because you are subscribed to the Google Groups "Electric
VLSI Editor" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to [email protected].
For more options, visit https://groups.google.com/d/optout.
