Thanks Sir It is working I am dong layout of this circuit. this is full adder circuit. I dont have any DRC & ERC error but I am unable to get the plot for Full adder Sum. i need you help Sir.
Here is my file On Sat, Oct 14, 2017 at 4:15 AM, Gavin Abo <[email protected]> wrote: > I think the NCC error "vout in Cell:test_1:r_divider" in the sch box may > be indicating that your schematic has a vout wire, but it could not find > the matching one on the layout. So your layout may be missing vout or it > might be mislabel (a typographical error). To more easily determine the > cause, you would have to send the jelib file. > > > On 10/6/2017 9:27 PM, sujan kanti wrote: > > > > On Friday, October 6, 2017 at 10:36:36 PM UTC+8, sujan kanti wrote: >> >> Hello Sir, >> I followed everything according to Dr. Jacob tutorial 1. At the time of >> simulation i found this error.How can I repair it? please help me. >> >> I have attached the problem >> > -- > You received this message because you are subscribed to a topic in the > Google Groups "Electric VLSI Editor" group. > To unsubscribe from this topic, visit https://groups.google.com/d/ > topic/electricvlsi/tkyE5fgf-cE/unsubscribe. > To unsubscribe from this group and all its topics, send an email to > [email protected]. > For more options, visit https://groups.google.com/d/optout. > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
tutorial_2.jelib
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