I've been following this thread about ESD testing and the PPS debate.
I would like to inject my point of view on the subject.

So far most of what I have read addresses the need for speed.
This is great for the test lab/house; to be able to slam through the process
in a quest to get it done quick for the sake of process throughput, but for
the purpose of determining if an EUT is immune to a pulse stimuli with
respect to possible entry points, I remain skeptical.

I suppose what I am alluring to is debugging for quality, but then, isnt the
purpose of compliance testing to 'test to fail' rather than test to pass?
This may depend on the lab itself.  With the PPS issue, I submit that from
at least the quality point of view it may depend on the type of product you
are testing and the functional test program that the EUT is operating.

For example, as an OEM (to a few of you out there) and direct mfr. we want
to be as thorough as possible because we want to make a quality product and
when we put "CE" on it, we mean it.  We do not want our customer to find a
problem with our products during their followup testing (not everyone
retests a CE marked product).  To ensure quality, we test our cabinet
products for a full day or two in the ESD lab (much more if it fails).  Many
times we have student interns who do this, but sometimes our experienced lab
techs do the job.  Nevertheless, ESD testing (particularly on our disk
arrays) is done very slowly because a rack mount version EUT can be loaded
with up to 154 disk drives ranging in capacity from 9 to 180Gb while using a
transfer block size ranging from 512 bytes to 256Kb.  The result is massive
overhead to response.

The exercise program for a device such as this (we call it smash/hammer)
performs a chained series of write/read/verify operations.  The tasking
packets may be buffered through a storage attached network (SAN) director
and thus the operations can be lengthy and/or latent in the outcome
reporting in the error daemon.  The only way for our test personnel to
determine if a failure has occurred is to monitor the screen of the EUT's
host pc to visually verify no errors have occured before proceeding to the
next zap.  This can take seconds to minutes after a stimuli is applied.
If such ESD testing were performed too rapidly, the operator can overlook a
failure, and its location.  There may be dozens of stimuli injection points
to be tested and thus the relative location on the EUT where the failure
event occurred can be overlooked.

Fortunately, the standard has provision for variety..

Thank-You,

Kyle Ehler  KCOIQE
<mailto:kyle.eh...@lsil.com> 
Assistant Design Engineer
LSI Logic Corporation
3718 N. Rock Road
U.S.A.  Wichita, Kansas  67226
Ph. 316 636 8657
Fax 316 636 8321

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