David,
I would add my voice to the notes below. In particular it was for
keyboards, and we tested at discrete steps. 2, 4, 6, 8, and then jumped in 4K
increments to 12, and 16 - occasionally to 20K for a specific customer
requirement. HP for example.
We too noted failures at lower levels that did not repeat at higher
levels. Principally in the 2 to 8K range, because at the higher levels we
changed the acceptance level from not sending out false codes to just not
locking up the processor.
These were principally in the air discharge mode - but repeatable
within the 20 discharges at each test point.
By the way I enjoyed the article you sent me on the arc length testing
- it at least gives me insight on why the method is presumed to simulate how an
actual human/metal ESD event occurs - through air. The data was presented for
5 Kv, but I couldn't tell whether it could also be used for different levels.
Sorry, I know from an empirical standpoint you need the data in your
hands not just recollection of events, but those tests were done for a
different company - but enough voices saying the same thing provide a strong
argument for confirming or denying the presumption scientifically. That sounds
like its right up your professorial ally and lord knows you have to have some
unwitting undergrads you could trick into the process.
Certainly would be ideal if it did, or that some adjustment mechanism
could be applied to a simulator for each voltage. That would allow for much
more automated testing.
Gary
-----Original Message-----
From: Scott Douglas [mailto:dougl...@naradnetworks.com]
Sent: Wednesday, June 12, 2002 5:01 AM
To: Pommerenke, David
Cc: EMC-PSTC
Subject: RE: IEC 61000-4-2 ESD & 61000-4-5 Surge lower levels
David,
Have been (still am) out of the office testing this week.
I am sorry to say that I cannot provide hard data to support my comments.
That experience was two lifetimes ago at a different employer. It happened
on more than one product model and on more than one of each model. I do
know that we would make 50 discharges at each test point. And, there were
more than ten test points on each model. Not every test point would exhibit
the problem, but those that did were consistent, something like 60% of
discharges would cause the system display to scramble. The peak failure
voltage was around 1.8 kV, with only a very few failures at 4 kV and none
at 8 or 15 kV. All were in contact mode.
This was all engineering work prior to official test house testing. We
identified the problems and made changes and re-tested. Once we got all
tests to pass, we would go for the official test. We had several of these
type of problems. Once was the scrambled (actually went black) LCD display.
Solved by shielding the cable to the display and termination resistors on
the display PCB. Another time was black lines in the recorded output (film
recorder products). This was corrected by proper grounding of the I/O
connector shell. Third time was system hang-up. If I recall this one
correctly, we added decoupling caps to chassis ground at the I/O connector
on the mother board. In all cases, the problems were at mid level tests,
usually 2 or 4 kV, rarely at 8 kV, and never at 15 kV.
Scott
At 08:33 PM 6/10/02 -0500, you wrote:
>Dear Scott,
>
>(1)
>I have looked at quite a bit of literature that plots
>
> Failure propatibility vs. Stress level in contact mode like testing
>
>and have seen very few none-monotonic EUTs that show the none-monotonic
>behavior over a larger voltage range.
>
>(2)
>In my five year test practise at HP, I have only seen one EUT that failed
>at lower levels and passed at higher levels in contact mode.
>
>
>If you have data that shows"As others have said, I have seen numerous
>failures at less than the maximum required test voltage while the same
>system passes at the max required voltage." please share that data with me
>if it is in contact mode and if the number of discharges at each level is
>large enough to obtain an acceptable confidence level.
>
>Regards
>
> David Pommerenke
>
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