On Sun, 22 Apr 2012, Andrew wrote:

Date: Sun, 22 Apr 2012 02:20:51 +0300
From: Andrew <parallel.kinemat...@gmail.com>
Reply-To: "Enhanced Machine Controller (EMC)"
    <emc-users@lists.sourceforge.net>
To: "Enhanced Machine Controller (EMC)" <emc-users@lists.sourceforge.net>
Subject: Re: [Emc-users] BLDC on 7i43 + 7i39 + linear motors

22 ???????????? 2012 ??. 02:04 Peter C. Wallace <p...@mesanet.com> 
??????????????:

Minimum period depends on how many I/O cycles you do and how much of the
host cycles you are willing to burn up doing I/O. with the parallel ports
I've tested with, I get between 3-6 Usec of I/O time for each 32 bit
register read/write on the EPP interfaced 7I43. So a three axis system may
have about 18-20 I/O cycles you would use about 54 to 120 usec of host time
doing EPP I/O

for a simple 3 or 4 axis system 4KHz may be possible (note: the 7I43 is
the slowest FPGA card we make due to the EPP interface ~8-12 times slower
than the PCI cards)


250000ns seems ok for one axis. Tomorrow I'll try all 3.


Tuning a voltage mode (or current mode = torque mode) drive is tricky you
will need a fair amount of P and D and FF1. The higher the sample rate the
better for phase margin (which will allow high stable gain). Also tuning
should be done with the carriage loaded and FF1 especially should be tuned
with the final motor voltage as FF1 is motor voltage dependent on a a
voltage mode drive

Already doing 1m/s with 40m/s2 acceleration, not so bad. But still have to
tune pid better, max error is up to 1mm. When I add D, much noise appears
on PID output.

Are you using the encoder velocity output to feed to the pid components fb-deriv pin?

If not already doing this, this can improve the D noise situation

Generally linear motors are well-controlled, I hope it's possible to
decrease f-error to 0.1-0.2mm. I probably should increase PWM frequency,
now it's 15000.
Thanks for your help.

Andrew

Peter Wallace
Mesa Electronics
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