On Mon, 5 Jun 2017, Bertho Stultiens wrote:

Date: Mon, 5 Jun 2017 16:20:03 +0200
From: Bertho Stultiens <ber...@vagrearg.org>
Reply-To: "Enhanced Machine Controller (EMC)"
    <emc-users@lists.sourceforge.net>
To: "Enhanced Machine Controller (EMC)" <emc-users@lists.sourceforge.net>
Subject: Re: [Emc-users] RPI saga continues - SPI probably solved

On 06/04/2017 06:15 AM, john mcintyre wrote:
Your saga continues, you must be related to a bulldog? ,once locked
on  it cannot let go.

Isn't this what you call a challenge?


Anyway, I've fixed a couple of things, like endianness, which I did
wrong in the previous versions. This implementation is hard-coded to use
the RPI hardware peripherals. Also, you can now attach to SPI0 or SPI1
ports on the 40-pin header and you may choose any CE line you wish
(updated man page also attached).

My tests so far have seen stable results, timing wise, although I cannot
test functionally on a real system (lacking a 7i90 in my inventory).
Though, the timing has improved with respect to the original version.

Read and write SPI clock frequencies may be different now. This will
help to overcome the SPI round-trip delay while reading (just lower the
read frequency setting), or when you want buffers on the SPI lines.

So, if anybody wants to have a go and test this, please do so and tell
me how it goes. In the meantime... need to get my hands on a 7i90 (and
upgrade the mill at the local hackerspace).

--
Greetings Bertho

(disclaimers are disclaimed)


Thank you for working on this! The ability to set the clock speed should be especially valuable. It means I can make a Async SPI interface version of the firmware (as opposed to the current hardware clocked version), that oversamples/digital filters the input data and clock for better noise resistance. This will probably require lowering the SPI clock to say 16 MHz
to accomodate the increased turnaround delays from the digital filtering.

Peter Wallace
Mesa Electronics


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