> 
> > 2) Will there be an added provision to put the CW keying downstream of 
> > the software (I'm thinking of a design point where the software transmit 
> > (in cahoots with this option) really was "continuous wave" and the key 
> > plugged in downstream far enough to actually do the On/Off keying in the 
> > classical way?
> 
> The Janus board does nothing special in this regard.  It is just a 
> four-in four-out ADC/DAC system that we tried to make high performance 
> for SDR applicaitons.
> 
> CW timing issues are a function of how the CW mode is implemented in 
> PowerSDR.


Well perhaps not. I was expecting that we may have a latency problem with the 
Janus + Ozy combination when using CW. We have still to stress test this with 
the latest version of PowerSDR but initial test seem to indicate that the 
latency is very low.

If not there is an alternative that I tested some time ago. That is to 
generate the I/Q CW tones, with suitable shaping, in the FPGA. Since the FPGA 
can also control the PTT hardware, and you can create the side tone in the 
FPGA also, so there is no delay between closing the key and hearing the 
sidetone. The actual RF that goes to air can be delayed to take care of relay 
delays etc. This technique avoids the delays associated with going into and 
out of the PC when sending CW. 

The test code worked OK but I dropped it when we found that the performance of 
the USB interface to PowerSDR seems to be adequate at 30+ WPM CW.  

As I say, this is one item that we need to stress tested shortly.

73's Phil...VK6APH





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