Steve Meier wrote: > I am seeking good references for verilog, VHDL and spice syntext > specificaly with the idea of supporting hierarchical net lists.
Verilog HDL by Palnitkar has been good for reading how to use verilog better. It has a good reference book organization... appendices with lists that would be helpful coding netlist output details -- it was published 1996 so that will probably tell which year of standard it matches best. Principles of Verifiable RTL Design has descriptions of code aimed at verification, and style that lets you use checkers well, and the examples go for simulation speed, so simulation is useful for mdeling more than two seconds of run time... It has a long tutorial that would be useful to refer to as coding. John G -- Ecosensory Austin TX _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
