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I do not like that form WarnUnimpl being repeated all over the place. Can you try if something else works? - Nilay Vaish On June 28, 2013, 1:41 p.m., Christian Menard wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1939/ > ----------------------------------------------------------- > > (Updated June 28, 2013, 1:41 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > This is an implementation of the x86 int3 and int immediate instructions for > long mode according to 'AMD64 Programmers Manual Volume 3'. I did not do any > heavy testing, but it works fine with the Fiasco.OC micro kernel > (http://os.inf.tu-dresden.de/fiasco/). I'm not sure if the changes to the > decoder (one_byte_opcodes.isa) break the way Linux-syscalls are currently > treated. So please have a look at it. > > > Diffs > ----- > > src/arch/x86/isa/decoder/one_byte_opcodes.isa UNKNOWN > > src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py > UNKNOWN > > Diff: http://reviews.gem5.org/r/1939/diff/ > > > Testing > ------- > > Test runs with Fiasco.OC micro kernel (http://os.inf.tu-dresden.de/fiasco/) > > > Thanks, > > Christian Menard > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
