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It seems like the diff doesn't apply cleanly in RB. It happens from time to
time, it's kinda crap.
I think you probably don't want to add the 'default: Inst::INT(Ib);' to the
SE-mode case, just using 'Inst::INT(Ib)' as the default when FullSystemInt != 0
should suffice. I'd be very surprised if taking an interrupt in SE mode is
going to do anything sensible.
I think you should be able to do 'limm t1, imm, dataSize=8' instead of clearing
t1 first.
Also, are you sure the long mode test is correct? Isn't it supposed to be
something like this:
andi t0, t5, 0x1, flags=(EZF,)
br rom_label("longModeSoftInterrupt"), flags=(nCEZF,)
IIRC, the least significant bit of the handy m5 reg is 0 for long mode and 1
for the the legacy modes.
- Andreas Sandberg
On Oct. 21, 2013, 12:18 p.m., Christian Menard wrote:
>
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> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1939/
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>
> (Updated Oct. 21, 2013, 12:18 p.m.)
>
>
> Review request for Default.
>
>
> Repository: gem5
>
>
> Description
> -------
>
> This is an implementation of the x86 int3 and int immediate instructions for
> long mode according to 'AMD64 Programmers Manual Volume 3'. I did not do any
> heavy testing, but it works fine with the Fiasco.OC micro kernel
> (http://os.inf.tu-dresden.de/fiasco/). I'm not sure if the changes to the
> decoder (one_byte_opcodes.isa) break the way Linux-syscalls are currently
> treated. So please have a look at it.
>
>
> Diffs
> -----
>
> src/arch/x86/isa/decoder/one_byte_opcodes.isa 59c6f42dcb6d
>
> src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
> 59c6f42dcb6d
>
> Diff: http://reviews.gem5.org/r/1939/diff/
>
>
> Testing
> -------
>
> Test runs with Fiasco.OC micro kernel (http://os.inf.tu-dresden.de/fiasco/)
>
>
> Thanks,
>
> Christian Menard
>
>
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