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(Updated Oct. 21, 2013, 10:18 a.m.) Review request for Default. Changes ------- After my question on the mailing list I updated this patch. The instructions now just check if the CPU runs in long or in legacy mode and jumps to the corresponding rom labels. The Decoder was changed as well. Now should be able to handle linux syscalls (int 80) in SE mode as well as soft interrupts in FS mode. Repository: gem5 Description ------- This is an implementation of the x86 int3 and int immediate instructions for long mode according to 'AMD64 Programmers Manual Volume 3'. I did not do any heavy testing, but it works fine with the Fiasco.OC micro kernel (http://os.inf.tu-dresden.de/fiasco/). I'm not sure if the changes to the decoder (one_byte_opcodes.isa) break the way Linux-syscalls are currently treated. So please have a look at it. Diffs (updated) ----- src/arch/x86/isa/decoder/one_byte_opcodes.isa 59c6f42dcb6d src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py 59c6f42dcb6d Diff: http://reviews.gem5.org/r/1939/diff/ Testing ------- Test runs with Fiasco.OC micro kernel (http://os.inf.tu-dresden.de/fiasco/) Thanks, Christian Menard _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
