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Ship it! I'm happy with the explanation you just gave. Could you add that as a comment to clarify why the zero register is allocated in this way? - Andreas Sandberg On May 28, 2015, 4:38 p.m., Alexandru Dutu wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2851/ > ----------------------------------------------------------- > > (Updated May 28, 2015, 4:38 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10859:9c783a1367cd > --------------------------- > cpu: o3: Mapping the ZeroRegister for all hardware threads > This patch helps enabling SMT in x86 by mapping the ZeroRegister to one > physical register across all hardware threads. > > > Diffs > ----- > > src/cpu/o3/cpu.cc d02b45a554b52c68cce41e1b3895fb8582a639dd > > Diff: http://reviews.gem5.org/r/2851/diff/ > > > Testing > ------- > > Quick regressions passed for all ISAs. > > > Thanks, > > Alexandru Dutu > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
