----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2851/#review6557 -----------------------------------------------------------
Ship it! Looks good. I assume this means that the register ordering problem you outlined earlier turned out to be a non-issue. - Andreas Sandberg On June 22, 2015, 7:44 p.m., Alexandru Dutu wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2851/ > ----------------------------------------------------------- > > (Updated June 22, 2015, 7:44 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10864:716172760d78 > --------------------------- > cpu: o3: Mapping the ZeroRegister for all hardware threads > This patch helps enabling SMT in x86 by mapping the ZeroRegister to one > physical register across all hardware threads. > > > Diffs > ----- > > src/cpu/o3/cpu.cc 9141d87c7f71099d6256b179b7819eab878cbb67 > > Diff: http://reviews.gem5.org/r/2851/diff/ > > > Testing > ------- > > Quick regressions passed for all ISAs. > > > Thanks, > > Alexandru Dutu > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
