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(Updated June 22, 2015, 6:44 p.m.) Review request for Default. Changes ------- Actually, giving this a second thought I like better the compressed version of this patch after Andreas's suggestion. Initially I was overly concerned with the unorderred initial mapping this will bring and the extra debugging confussion, however initial mappings change and there should not be much debugging on the register renaming front. So a compact code is the way to go. Repository: gem5 Description (updated) ------- Changeset 10864:716172760d78 --------------------------- cpu: o3: Mapping the ZeroRegister for all hardware threads This patch helps enabling SMT in x86 by mapping the ZeroRegister to one physical register across all hardware threads. Diffs (updated) ----- src/cpu/o3/cpu.cc 9141d87c7f71099d6256b179b7819eab878cbb67 Diff: http://reviews.gem5.org/r/2851/diff/ Testing ------- Quick regressions passed for all ISAs. Thanks, Alexandru Dutu _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
