> On June 22, 2015, 9:59 p.m., Andreas Sandberg wrote: > > Looks good. I assume this means that the register ordering problem you > > outlined earlier turned out to be a non-issue. > > Alexandru Dutu wrote: > Actually, while doing more testing I remembered that this ordering has to > be enforced as the rest of the code that handles zero register exceptions > assumes the physical register assigned for the it is the same with the > architectural register. Is there a way to revert to the previous revision in > review board or discard the current one?
I don't know. I'd say that you don't need to worry. Just clarify the comment in the previous revision and push the change. - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2851/#review6557 ----------------------------------------------------------- On June 22, 2015, 7:44 p.m., Alexandru Dutu wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2851/ > ----------------------------------------------------------- > > (Updated June 22, 2015, 7:44 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10864:716172760d78 > --------------------------- > cpu: o3: Mapping the ZeroRegister for all hardware threads > This patch helps enabling SMT in x86 by mapping the ZeroRegister to one > physical register across all hardware threads. > > > Diffs > ----- > > src/cpu/o3/cpu.cc 9141d87c7f71099d6256b179b7819eab878cbb67 > > Diff: http://reviews.gem5.org/r/2851/diff/ > > > Testing > ------- > > Quick regressions passed for all ISAs. > > > Thanks, > > Alexandru Dutu > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
