> On Oct. 16, 2015, 2:53 p.m., Nilay Vaish wrote: > > configs/example/fs.py, lines 220-223 > > <http://reviews.gem5.org/r/2986/diff/7/?file=50321#file50321line220> > > > > I think all of this code should be in MemConfig.py. > > Andreas Hansson wrote: > This is not as clear cut as you make it sound Nilay. The memory > controller itself represents a single channel, and traditionally the > MemConfig functions have created a number of channels, and attached them to a > crossbar (usually the system.membus). In the HMC case we are dealing with a > more complicated system, and you may even have different links connecting > different "systems". I am not objecting to moving things into MemConfig, but > "mem_type" is being slightly abused here as it normally refers only to the > subclass of DRAMCtrl. Here the string is being hi-jacked to also mean insert > a host-side controller and a number of serial links. I am tempted to suggest > we leave this out of this patch, and rather allow an option "Buffer-on-Board" > or similar, in addition to the mem_type.
I'll let Erfan and you decide how to organize the code here. I just do not like adding this code in fs.py. And I think HMC is not dependent on whether we are in fs or se mode. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2986/#review7380 ----------------------------------------------------------- On Oct. 18, 2015, 4:31 p.m., Erfan Azarkhish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2986/ > ----------------------------------------------------------- > > (Updated Oct. 18, 2015, 4:31 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11174:6e02b2208e16 > --------------------------- > mem: Simple HMC Model > > This patch enables modeling a complete Hybrid Memory Cube (HMC) device. It > highly reuses the existing components in gem5's general memory system with > some small modifications. This changeset requires an additional patch (2993) > for modeling the serial links. > > > Diffs > ----- > > configs/common/HMC.py PRE-CREATION > configs/common/MemConfig.py 3a4d1b5cd05c > configs/example/fs.py 3a4d1b5cd05c > src/mem/DRAMCtrl.py 3a4d1b5cd05c > src/mem/HMCController.py PRE-CREATION > src/mem/SConscript 3a4d1b5cd05c > src/mem/hmc_controller.hh PRE-CREATION > src/mem/hmc_controller.cc PRE-CREATION > src/mem/xbar.hh 3a4d1b5cd05c > > Diff: http://reviews.gem5.org/r/2986/diff/ > > > Testing > ------- > > gem5 compiles > fs.py executes and Linux boots correctly. > hmctest.py executes correctly, and stats correlate with cycle-accurate > simulation > > > Thanks, > > Erfan Azarkhish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
