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src/cpu/pred/bpred_unit_impl.hh <http://reviews.m5sim.org/r/47/#comment210> Shouldnt this *not* be hardcoded to 16, but instead the true RAS size? src/cpu/pred/bpred_unit_impl.hh <http://reviews.m5sim.org/r/47/#comment211> What happens if the RAS is full? is it right to just overwrite the next entry? src/cpu/pred/bpred_unit_impl.hh <http://reviews.m5sim.org/r/47/#comment212> If you miss on a BTB lookup and you've predicted taken, should you not instead stall (or have the option to stall) the CPU until branch resolution??? (I've got a patch for this option in another tree if people think that's useful) src/cpu/pred/bpred_unit_impl.hh <http://reviews.m5sim.org/r/47/#comment213> I'm not a fan of this localBP vs tournamentBP comparison we do everytime we need to lookup or update the predictor... Why isnt there a base predictor class that the localBP and the tournamentBP derive from? Eventually if someone wanted to substitute the predictor or implement something else (e.g. no predictor at all and always predict false), all you would need to do is pass that as a SimObject(?) to the branch prediction unit and it would be plug-n-play. - Korey On 2010-07-09 18:08:18, Timothy Jones wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/47/ > ----------------------------------------------------------- > > (Updated 2010-07-09 18:08:18) > > > Review request for Default. > > > Summary > ------- > > BranchPred: Take the branch predictor out of O3CPU and make it a stand-alone > SimObject. This then allows the same branch predictor to be shared amongst > several CPUs. > > This patch is unfinished. I would like to take the branch predictor out of > the inorder CPU as well, but want comments on whether this is the best > approach to take first. > > > Diffs > ----- > > src/cpu/o3/O3CPU.py 249f174e6f37 > src/cpu/o3/SConscript 249f174e6f37 > src/cpu/o3/bpred_unit.hh 249f174e6f37 > src/cpu/o3/bpred_unit.cc 249f174e6f37 > src/cpu/o3/bpred_unit_impl.hh 249f174e6f37 > src/cpu/o3/cpu_builder.cc 249f174e6f37 > src/cpu/o3/cpu_policy.hh 249f174e6f37 > src/cpu/o3/fetch.hh 249f174e6f37 > src/cpu/o3/fetch_impl.hh 249f174e6f37 > src/cpu/pred/BaseBPredUnit.py PRE-CREATION > src/cpu/pred/SConscript 249f174e6f37 > src/cpu/pred/base.hh PRE-CREATION > src/cpu/pred/base.cc PRE-CREATION > src/cpu/pred/bpred_unit.hh PRE-CREATION > src/cpu/pred/bpred_unit.cc PRE-CREATION > src/cpu/pred/bpred_unit_impl.hh PRE-CREATION > src/cpu/pred/builder.cc PRE-CREATION > > Diff: http://reviews.m5sim.org/r/47/diff > > > Testing > ------- > > > Thanks, > > Timothy > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
