On Sat, Jul 17, 2010 at 4:52 AM, Korey Sewell <ksew...@umich.edu> wrote: > > A hint for this is that the InOrderCPU was passing the nextPC to the branch > predictor instead of the PC, so there is a ras statement there that you'll > need to be aware of to update.
That seems odd... I assume you're suggesting that Tim switch the InOrderCPU to pass the PC instead, right? > Also, the BTB accesses use the asid instead of the tid (to accomodate > multithreading) so please dont remove that. I'm confused... are you trying to let threads that run in the same address space all share the same BTB entries? That might actually be a good idea, but I don't know that any real CPUs work that way. (Not that I have intimate knowledge, I'd just be surprised... the ASID generally has a lot more bits than the TID, esp. in x86 where the ASID is really just the page table base pointer.) Steve _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
