> > > > 1. An in-order CPU module with multi-threading (switching threads upon >> cache >> > accesses) based on TimingSimpleCPU >> This is probably #1 on the priority list >> > Is this inorder model detailed (in terms of pipeline stages, branch > prediciton, Functional Units, etc.)? >
No it's not detailed (so I guess it does not antiquate the actual inorderCPU model that you are developing). It's simply have multiple active thread contexts on a TimingSimpleCPU and the CPU switches among them upon memory accesses. > Is it functional within Full system mode? > I've only used it for system emulation mode. If your team is interested and can help me with fully system mode, I am willing to bring it to full system mode afterwards. Thanks, Jiayuan
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