> > > > 2. SIMD cores: Based on TimingSimpleCPU. > This sounds pretty interesting too. Does the ISA matter much, or do > you think it could be pretty generic? Did you add new instructions to > do things? >
Yes, I amended the Alpha ISA and added two instructions to mark the begin and end of branch divergences. I assume we can do the same thing for other ISAs. > > > 3. A parallel API for writing parallel benchmarks that run in system > > emulation mode. > So, this doesn't depend on #2? I assume that this is in syscall > emulation mode? This is pretty interesting. The one issue is that > there are already two? systems in m5 for doing parallel simulations > and we don't want to just throw the kitchen sink into m5. Have you > looked at the current m5threads stuff? Is there any overlap? > No it doesn't. Actually, #2 depends on this one. Yes, it's in syscall emulation mode. Thanks for the pointer, I'll take a look at m5threads. > > 4. A batch-simulation tool, which creates, manages, organizes, and > analyzes > > simulation tasks in batches. Written in Python. Good for space > exploration > > and sensitivity study. > Sure, I will write some documentation and send you a tarball. Thanks, Jiayuan
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