Hi yg,
On 29 April 2014 03:52, <[email protected]> wrote:
>
> Now it seems to me that all there is to do is reuse the mcode
> version and ADD transparent/parallel code that generates
> the gates netlist. For example, if you have something flagged
> as a signal, the mcode+ backend would generate object code
> for doing the operation AND generating the corresponding
> gate in the netlist, in parallel. It would be transparent !
>
> The output would be more bloated but
> it would actually generate the netlist (and ensure code coverage
> and identification of stuck values or their ranges)
> during the simulation of the actual circuit.
>
Does mcode+ really work this way? Sorry I'm not sure how this whole thing
works. If mcode+ is able to generate gate-level netlist for us, that would
be great. But does it do that really? Say you have a process with if-else
statements, some gates, and a clock. Would mcode+ generate an equivalent
gate-level circuit connecting each of these components correctly in the
form of a netlist? It requires quite some amount of semantic analysis in my
opinion. E.g.:
/* Input behavioural VHDL */
process(reset,clk) is begin
if reset then q<='0';
elsif rising_edge(clk) then q<=a xor b;
end if;
end process;
I would expect a generated netlist to look something like (structural VHDL
here, but could be in any other language):
-- example output gate-level netlist
architecture structural of rtl is
signal i_q:std_ulogic;
begin
u0: entity lib.dff(rtl) port map(rst=>reset, clk=>clk, d=>i_q, q=>q);
u1: entity lib.xor(rtl) port map(in0=>a, in1=>b, output=>i_q);
If mcode+ is able to do this, it's something worth taking a look. :)
How about having case statements, if-elsif-else, of with-select-when
statements? We need something that automatically creates the muxes.
> Better to start after semantic analysis.
>>
> I'll love to see a proof of concept of your approach :-)
>
> In any case, I think I'll need a Free
> full VHDL compliant analyser in the future.
>
I too would like to have a free (and open source) VHDL compliant synthesis
tool. :)
regards, daniel
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