In this model, d1 and d2 are essentially the same signal but q1 and q2 behave
differently. (A waveform image is attached). The reset behavior is curious as
well (but that's a bit more subtle).
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity reg is
end reg;
architecture rtl of reg is
signal clk, reset, d1, q1, d2, q2 : std_logic := '0';
begin
reset <= '1', '0' after 30 ns;
clk <= not clk after 10 ns;
d1 <= not d1 after 10 ns;
d2 <= d1;
process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
q1 <= '0';
q2 <= '0';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
---------------------------------------------------------
I don't have access to another simulator at the moment. If anyone has access to
ModelSim, Synopsys, etc., it would be interesting to compare the results.
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