> On Mar 28, 2015, at 5:52 PM, Adam Jensen <[email protected]> wrote:
>
> On Sun, 29 Mar 2015 09:34:40 +1300
> David Koontz <[email protected]> wrote:
>
>> There's also Nick Gasson's nvc analyzer/simulator, while not as feature rich
>> as ghdl easily adequate for this model. It also gives the same answer:
>
> Interesting.
>
>> From a hardware design perspective you have a symbol rate for d1/d2 that
>> doesn't match your clock rate. At best it's a phase detector telling us d1
>> occurs at or before clk and d2 occurs after clk.
>>
>
> That code snippet was devised to expose some behavior of the simulator rather
> than as a model of anything meaningful. I'm still exploring the character of
> GHDL - stability, boundaries, tolerances, etc. So far, I think it's an
> über-nifty tool.
Something I learned the hard way, having come to VHDL from a programmer
background: VHDL signals are *not* like programming language variables. (VHDL
variables are, though). If you do
foo <= 1;
bar <= foo;
bar acquires the previous value of foo, not the new one. A decent VHDL
textbook will describe why that is in great detail.
paul
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