On Fri, 2015-03-27 at 19:46 -0400, Adam Jensen wrote: > In this model, d1 and d2 are essentially the same signal but q1 and q2 behave > differently. (A waveform image is attached). The reset behavior is curious as > well (but that's a bit more subtle). >
Perhaps it helps to understand that there is an inherent race condition in the code (signal and clock assignments changing simultaneously) and the extra delta cycle on D2 illustrates how trivial (e.g. wire) delays can trigger the race to give varying results. In other words, the VHDL signal assignment timing mechanism isn't creating a problem here, it's just exposing one that's present in the design. Which IMO is a Good Thing. -- Brian _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
