Brian does a wonderful explanation on stackoverflow: http://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant/13956532#13956532
"No event will ever occur while a process is running!" On 30/03/2015, at 8:19 am, Adam Jensen <[email protected]> wrote: > On Sun, 29 Mar 2015 13:53:54 -0400 > Paul Koning <[email protected]> wrote: > >> Something I learned the hard way, having come to VHDL from a programmer >> background: VHDL signals are *not* like programming language variables. >> (VHDL variables are, though). If you do >> >> foo <= 1; >> bar <= foo; >> >> bar acquires the previous value of foo, not the new one. A decent VHDL >> textbook will describe why that is in great detail. > > It depends upon where they occur. > -------------------------------------------------------------------------- > library ieee; > use ieee.std_logic_1164.all; > entity example is > end entity example; > architecture test of example is > signal wire_seg1, wire_seg2, wire_seg3, wire_seg4 : std_logic := '0'; > signal delay_element, clk : std_logic := '0'; > signal lfsr : std_logic_vector(3 downto 0) := (others => '1'); > begin > clk <= not clk after 10 ns; > process (clk) is > begin -- process > if (clk'event and clk = '1') then > lfsr(3) <= lfsr(1) xor lfsr(0); > lfsr(2 downto 0) <= lfsr(3 downto 1); > end if; > end process; > wire_seg1 <= lfsr(0); > wire_seg2 <= wire_seg1; > delay_element <= wire_seg2 after 3 ns; > wire_seg3 <= delay_element; > wire_seg4 <= wire_seg3; > end architecture test; > -------------------------------------------------------------------------- > > Or, written differently (but logically equivalent): > > -------------------------------------------------------------------------- > library ieee; > use ieee.std_logic_1164.all; > entity example is > end entity example; > architecture test of example is > signal wire_seg1, wire_seg2, wire_seg3, wire_seg4 : std_logic := '0'; > signal delay_element, clk : std_logic := '0'; > signal lfsr3, lfsr2, lfsr1, lfsr0 : std_logic := '1'; > begin > clk <= not clk after 10 ns; > process (clk) is > begin -- process > if (clk'event and clk = '1') then > lfsr3 <= lfsr1 xor lfsr0; > lfsr2 <= lfsr3; > lfsr1 <= lfsr2; > lfsr0 <= lfsr1; > end if; > end process; > wire_seg1 <= lfsr0; > wire_seg2 <= wire_seg1; > delay_element <= wire_seg2 after 3 ns; > wire_seg3 <= delay_element; > wire_seg4 <= wire_seg3; > end architecture test; > -------------------------------------------------------------------------- > <example.png>_______________________________________________ > Ghdl-discuss mailing list > [email protected] > https://mail.gna.org/listinfo/ghdl-discuss _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
