On Sun, 29 Mar 2015 09:34:40 +1300 David Koontz <[email protected]> wrote:
> There's also Nick Gasson's nvc analyzer/simulator, while not as feature rich > as ghdl easily adequate for this model. It also gives the same answer: Interesting. > From a hardware design perspective you have a symbol rate for d1/d2 that > doesn't match your clock rate. At best it's a phase detector telling us d1 > occurs at or before clk and d2 occurs after clk. > That code snippet was devised to expose some behavior of the simulator rather than as a model of anything meaningful. I'm still exploring the character of GHDL - stability, boundaries, tolerances, etc. So far, I think it's an über-nifty tool. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
