In <4e24b31c.5080...@phoenixsoftware.com>, on 07/18/2011 at 03:26 PM, Edward Jaffe <edja...@phoenixsoftware.com> said:
>Absolutely! There is a multi-stage pipeline that allows the processor >to get ahead of the current instruction's execution to fetch and >decode instructions, resolve addresses, fetch operands, etc. in >advance of the actual instruction execution. That doesn't address my question. The questions are when the processor starts filling in a new segment of the pipeline for a branch and whether it takes the opcode into account. Keep in mind that there is not a separate general register for the target address mode. -- Shmuel (Seymour J.) Metz, SysProg and JOAT ISO position; see <http://patriot.net/~shmuel/resume/brief.html> We don't care. We don't have to care, we're Congress. (S877: The Shut up and Eat Your spam act of 2003) ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html