Where do you find such detailed descriptions?  Patent application?  System 
journal?  NDA material?  You can tell me, but then you'ld have to kill me?

Bill Fairchild
Rocket Software

-----Original Message-----
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of 
Edward Jaffe
Sent: Friday, July 22, 2011 1:19 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: running Assembler I/O macro code as AMODE 31, RMODE ANY

The last time I thoroughly studied/investigated System z branch prediction logic
(BPL) was on the z9.

On that model, the BPL runs early in the pipeline, before instruction decode, 
and it essentially runs asynchronously to the rest of the pipeline. It 
prefetches instructions and predicts direction and target based on the path it 
thinks the rest of the pipeline will be later executing. It puts those 
prefetched streams into fairly large instruction buffers awaiting when they 
might be needed by the decode logic.

The BPL logic itself uses what appears to be a unified Branch Target Buffer and 
Direction Buffer (they are physically built of separate arrays but are 
logically the same). The BTB contains 8K entries. Being clever, IBM decided not 
to 'remember' not-taken conditional branches, thus allowing the BTB to appear 
much bigger than it really is. This was considered a reasonable performance 
trade-off (the rationale for keeping not taken branches in the BTB is to more 
accurately handle branches that frequently change direction). The z9 BTB uses a 
strongly-taken, weakly-taken approach for each branch.

Another clever thing IBM did on the z9 was to implement "just in time" 
prefetching down non-predicted branch paths to enhance performance. So if the 
hardware predicts a branch will be not taken, it prefetches the taken-path just 
before the branch direction is resolved in the execution stage of the pipeline. 
So if it was predicted incorrectly, the taken-path will be in a "recovery 
instruction buffer" where it could be sent into the decoder on the next cycle.

Slick! :-) 

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