Michael,

It sounds like you are issuing the SETFRR under your TCB which is going to 
SCHEDULE your SRB. This is not necessary and will almost certainly cause you 
problems, such as the 0F8 abend, and this FRR will not protect your SRB.

FRR's can be used to establish a recovery environment for a TCB, but I don't 
think you really need one here. If you do need such an environment, I would use 
an ESTAEX.

You can choose to use an FRR with your SRB, or, you can just let it percolate 
back to your TCB, as Chris mentioned. If you do want an FRR for your SRB, you 
can just set its address in the SRBFRRA field or you can issue your own SETFRR 
rearly in the SRB code. I would also suggest issuing an SRBTIMER macro to catch 
any loops you might have.

Like the Binjamin and Chris, I wonder what you're trying to accomplish here. It 
sounds like this is your first foray into this sort of coding, but it also 
appears that you haven't read all of the background material in the z/OS 
Authorized Programming Guide, which I suggest you should do. In there are the 
answers to all of the questions you've been asking here.

If you are determined to push ahead, I'm hoping you are testing on a sandbox 
system. 

Please be more communicative with your objectives here.

Tom

-----Original Message-----
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of 
Binyamin Dissen
Sent: Tuesday, October 18, 2011 3:10 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

On Tue, 18 Oct 2011 00:26:08 -0400 Micheal Butz <michealb...@optonline.net>
wrote:

:>I am trying to issue a branch entry form of  a macro in a other address 
:>space since the specifications say PASN=HASN=SASN

Which macro?

:>SRB was the only way to go, the branch entry form of the macro was the only 
:>code in the SRB I figured I would set up a FRR 

:>So that if anything goes wrong RTM would give control to the FRR I could 
:>examine the SDWA for any problems

Have you done FRR's before? ESTAEs? If not, you might be biting off more than 
you can chew with testing a FRR and SRB's at the same time.

Under which conditions will you recover?

You might want to set it up so that the SRB will abend your issuing task. 

Also, I don't get the connection between what you are doing and a non-reentrent 
TSO command.

Try to give details on WHAT you are trying to accomplish - not how you are 
trying to do it.

:>-----Original Message-----
:>From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf 
:>Of Chris Craddock
:>Sent: Tuesday, October 18, 2011 12:05 AM
:>To: IBM-MAIN@bama.ua.edu
:>Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH :> 
:>No, you werent where you thought you were in the code. The system doesn't 
:>lie about what happened.  You can't issue any SVC instructions while you 
:>have an FRR on the stack, regardless of what kind of FRR you have. And don't 
:>forget you may be calling other system services whether you're aware of it 
:>or not. 
:>
:>Leaving aside the general undesirability of testing SRB code  by trial and 
:>error, If you did manage to get the SRB scheduled then two interesting 
:>things are happening to you. First you have another independent unit of work 
:>running (the SRB) which will muddy the waters because any error that befalls 
:>the SRB will be reflected back on the TCB you're running under so your 
:>debugging information is going to be quite confusing. 
:>
:>Frankly you're kind of stumbling around in a coal mine with a flashlight 
:>even trying this. I would usually give a little sermon about all the things 
:>that can go horribly wrong. I will spare you that but here's the rub -- 
:>there's not a lot of chance you're going to suddenly converge on a solution 
:>that works. Tell us what problem you're trying to solve and maybe we can 
:>help you without trashing your system. 
:>
:>Sent from my iPad
:>
:>On Oct 17, 2011, at 10:07 PM, Micheal Butz <michealb...@optonline.net>
:>wrote:
:>
:>> I didn't issue any SVC
:>>
:>> The code blew up under TESTAUTH at the fifth instruction after the :>> 
expansion of the SETFRR macro :>> :>> I normally get 0F8 when I am in XMEM mode 
and issue a SVC I didn't abended
:>> on a SVC I abended whitin STM of the SETFRR inst    
:>>
:>> -----Original Message-----
:>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On 
:>Behalf :>> Of Lizette Koehler :>> Sent: Monday, October 17, 2011 10:54 PM :>> 
To: IBM-MAIN@bama.ua.edu :>> Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 
00000014 under TESTAUTH :>> :>>> Hi, :>>> :>>> :>>> :>>> I am trying to 
establish a FRR in a TSO command processor program that is :>> not re- :>>> 
entrant this is because :>> :>>> :>>> Later I schedule a SRB and I want to use 
the routine I established as a :>> FRR, as  input :>>> to the SRBFRRA parameter 
:>>> :>> :>> Did you review the abend and code?
:>> S0F8 - 14 - THE SVC ISSUER HAD AN ENABLED UNLOCKED TASK MODE FRR.       
:>>            IE. EUT=YES WAS SPECIFIED ON THE SETFRR MACRO.
:>>
:>> Did it help?
:>>
:>> Are you a member of the assembler language newsgroup?  You might have 
:>better
:>> response there or better assistance.   assembler-l...@listserv.uga.edu
:>
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--
Binyamin Dissen <bdis...@dissensoftware.com> http://www.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel


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