On 6 March 2012 16:00, Micheal Butz <michealb...@optonline.net> wrote:
> The Doc for LAE says the inst the functionality is dependent on PSW bits 16 > 17 address space control bits these are set by the SAC inst > > So my original question remains does > > Should address space control buts be set via the sac before executing the LAE It depends on what you are trying to accomplish, and you really haven't said much about that. The LAE instruction is designed so as to set the target general and access registers to values that meet the reasonable expectations for the translation mode you are executing with. If you subsequently continue in or change to AR mode, the target registers will have been be set so as to address the same data as the source of the LAE instruction, had it been a storage referencing instruction such as load (L). If you continue in or change to something other than AR mode, the access register will play no part in data addressing, but the general register will have been loaded appropriately regardless. Tony H. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
