On Wed, 21 Nov 2007 18:14:56 +0800 Johnny Luo <[EMAIL PROTECTED]> wrote:
:>I was reading the manual for an explanation of CPU lock: :>CPU lock -- provides MVS-recognized (valid) disablement for I/O and :>external interrupts. :>The manual gives a further explanation: :>MVS does not guarantee preservation of the interrupt status of :>programs that explicitly disable for I/O and external interrupts :>through the STNSM instruction. :>What does 'does not guarantee' mean? I would presume that should the code be interrupted (PIC-10/11, restart, etc.) the masking bits in the old PSW may not be preserved and upon redispatch the PSW may be enabled for interrupts. Basically it means - under MVS, do not use STNSM - take the CPU lock. -- Binyamin Dissen <[EMAIL PROTECTED]> http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
