In a message dated 11/21/2007 5:31:09 A.M. Central Standard Time,  
[EMAIL PROTECTED] writes:

:>The  manual gives a further explanation:

:>MVS does not guarantee  preservation of the interrupt status of
:>programs that explicitly  disable for I/O and external interrupts
:>through the STNSM  instruction.

:>What does 'does not guarantee' mean?

I would  presume that should the code be interrupted (PIC-10/11, restart, 
etc.)
the  masking bits in the old PSW may not be preserved and upon redispatch  the
PSW may be enabled for interrupts.

Basically it means - under  MVS, do not use STNSM - take the CPU lock.

There must be more to it than that.  The IBM module IOSVSSCQ (BALR-ed  to in 
the expansion of the STARTIO macro) has a STNSM PSASYMSK as its 3rd  
instruction (preceded only by a BASR and AHI in the system I am using).  I  
have 
studied the source code of this module extensively, and remember that later  in 
this 
module the UCB lock for the device involved is obtained.  What  happens if an 
interrupt occurs between the STNM and the SETLOCK?  I don't  think that IOS 
would like it if its interrupt status was not preserved.   The STARTIO macro 
can be issued by any authorized code whether it is enabled or  disabled and 
whether it holds a lock or not.
 
Another clue is that in the PSA DSECT the comment on the PSASYMSK byte says  
this:  "This field will be used in conjunction with the STNSM instruction  to 
place IOS channel scheduler into a disabled state ..."  If you scan this  
whole DSECT for "STNSM" you will find several such fields that are used to  
hold 
the system mask upon doing a STNSM and even more STOSM instructions whose  
operands are the PSA bytes where various STNSMs saved the mask.
 
Translation:  IBM's use of the STNSM to disable interrupts explicitly  within 
the nucleus is rife, so why do they externally document that it should  not 
be done?

 
Bill  Fairchild
Franklin, TN



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