In <[EMAIL PROTECTED]>, on 12/31/2007
at 02:13 PM, Tom Marchant <[EMAIL PROTECTED]> said:
>When processors srarted to include High-Speed Buffers, now commonly
>called cache,
I don't recall seeing "high speed buffer" in print until long after
"cache" was common.
>any published timings became very difficult to determine.
They started to get complicated before that, but I'll agree that cache and
TLB considerations made it worse.
>These effects are one of the biggest reasons why instruction timings
>tend to vary.
By the 3165 timings were very complex even when all data were in cache.
--
Shmuel (Seymour J.) Metz, SysProg and JOAT
ISO position; see <http://patriot.net/~shmuel/resume/brief.html>
We don't care. We don't have to care, we're Congress.
(S877: The Shut up and Eat Your spam act of 2003)
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