On Dec 31, 2007, at 2:13 PM, Tom Marchant wrote:
------------------SNIP---------
When processors srarted to include High-Speed Buffers, now commonly
called
cache, any published timings became very difficult to determine. When
memory references were simple real memory references, the time
required for
each was easily determined. With the HSB, a memory reference took
some
number of clock cycles it the data were in the HSB and longer id
they had to
be fetched from main store. Sometimes still longer if a line in
the buffer had to
be written back to main store first.
Of course, virtual address translation addes yet another layer of
complexity to
the time required to access storage. Worst case is a memory
reference to get
the segment table entry, another to get the page table entry and a
third to
access the storage required. Then if the data referenced crosses a
segment
boundary, another memory reference to get the next segment table
entry and
the page table entry. Translation Lookaside Buffers are used to
keep these
references to a minimum.
These effects are one of the biggest reasons why instruction
timings tend to
vary.
--
Tom Marchant
Tom,
Of course you are correct and that is (probably) why the 1419 ended
up in the DC graveyard. Thanks for reminding us of the history. I had
just remembered working on timing of a specific machine.
To refresh my memory was the 370 the first public machine that used
the HSB? My memory says yes but as we have seen the POPS and FUNC
manual are indeed different. There were quite a few machines I had no
exposure to like the 44 and the 67 and the (1)95 among others
Ed
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