The following message is a courtesy copy of an article that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.
[email protected] (Timothy Sipples) writes: > And it's a little tough to pin down when SMP began, because engineers > are going to quibble about the definition and exact characteristics > that qualify. However, some notable systems include a version of the > System/360 Model 65 (with dual processors -- I've seen this referred > to as the "M65MP"), and this option carried into the Model 67. The > Model 65 started shipping in November, 1965, although I'm not sure > exactly when the M65MP variant shipped, and I don't know much about > it. Probably not much later, if at all, since the Model 67 shipped in > August, 1966. 360/67 uniprocessor was very much a 360/65 uniprocessor with address relocation (virtual memory) hardware added (with virtual memory mode providing for both 24-bit and 32-bit virtual addressing). 360/67 multiprocessor was much more complex than 360/65 multiprocessor. 360/65 multiprocessor had processors sharing all the same memory ... but each processor had its own "private" channels. To simulate a multiprocessor I/O configuration ... multi-channel controllers were used ... with the channels from the different processors connecting into "shared" controllers (usually with the same address configuration). 360/67 multiprocessor had a lot more to it, including a "channel controller" box ... and in multiprocessor operation ... all processors addressed all channels. part of the control registers were used to address the switch settings in the channel controller (which controlled the configuration of the channels as well as the memory banks). In at least one three-way 360/67 multiprocessor shipped, the control registers were not only used to sense the "channel controller" switch settings ... but were also able to change the hardware configuration settings. Originally there was 360/60 (and 360/70) with slower memory ... and a model with virtual memory added. I remember seeing an early virtual memory reference manual describing standard multiprocessor architecture was for 4-way (which was reflected in the control register and channel control description). All the processors were renumbered when 750mic memory replaced the slower speed memory. Howerver, I don't anything about 360/65 multiprocessor was for anything other than two-way. copy of the 360/67 function characteristics (including description of the channel controller box, control register values, etc) http://bitsavers.org/pdf/ibm/360/funcChar/GA27-2719-2_360-67_funcChar.pdf the corporate "official" operating system for the 360/67 was tss/360 ... directory with various TSS/360 documents: http://bitsavers.org/pdf/ibm/360/tss/ some amount of 360/67 features weren't seen again until 370xa. the science center had started a project to do a virtual machine implementation ... and first attempted to get a 360/50 to modify with virtual memory hardware ... but because so many 360/50s were going to the FAA air traffic control project ... had to settle for a 360/40. this was used to develop cp/40. when the science center was able to obtain a 360/67, cp/40 morphed into cp/67. ... directory with at least one manual: http://bitsavers.org/pdf/ibm/360/cp67/ cp67 was very much a skunk works project ... with numerous corporate attempts from various quarters, at various times, to periodically terminate it. slightly related recent post http://www.garlic.com/~lynn/2009.html#6 mvs preemption dispatcher lots of the early 360/67 lore can be found in Melinda's VM history document ... a number of versions in various formats can be found here: http://www.princeton.edu/~melinda os/360 mp/65 smp implementation basically had a single global system "spin-lock" ... applications could run concurrently on both processors, but at entry to the supervisor ... TEST&SET instruction was used in attempt to obtain the global lock. If the other processor had the lock, it would just branch back to TEST&SET and repeat the operation until the other processor released the lock (basically only a single processor executing in the supervisor at a time). charlie was doing fine-grain multiprocessor locking work on cp67 at the science center ... lots of past post mentioning science center http://www.garlic.com/~lynn/subtopic.html#545tech when he invented the compare&swap instruction (chosen because CAS are charlie's initials) ... lots of past posts mentioning SMP and/or compare&swap http://www.garlic.com/~lynn/subtopic.html#smp there was then discussions with the 370 hardware architecture group to have them include compare&swap instruction ... however it was initially rejected ... with the comment that the "favorite son operating system" people saw no need for anything more than the "test&set" instruction (see above comment about global system spin-lock). The architecture group said that in order to justify compare&swap instruction for 370 ... other than SMP system lock use was needed. Thus was born the description (still in principles of operation) for using compare&swap instruction in coordinating application multithreaded/multiprogramming operation (whether or not running in multiprocessor environment). http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/DZ9ZR003/A.6?SHELF=DZ9ZBK03&DT=20040504121320 -- 40+yrs virtualization experience (since Jan68), online at home since Mar70 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
