The following message is a courtesy copy of an article that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.
tz...@attglobal.net (Tony Harminc) writes: > In particular, the 65MP did not have a programmable prefix register to > relocate low storage for each CPU the way S/370 and later do. Rather, > the prefixing was either ON or OFF for each CPU, and controlled by a > front panel switch. If OFF, references to the low 4KB of storage went > to the low 4KB; if ON, they went to the high 4KB of installed storage. > So this would make life difficult for more than two CPUs. re: http://www.garlic.com/~lynn/2009.html#28 the Z/10 and timers. 360/67 smp had a programmable prefix register similar to 370 (reference the 360/67 functional specification mentioned in previous post) ... i.e. references to "real" page zero were remapped to the page address in the prefix register ... as a result ... each processor could have its own, unique "page zero" (when otherwise all other addresses on all processors mapped to the same storage locations). for 370 smp prefix register, "reverse" mapping was added ... i.e. references to the real page address (specified in the prefix register) were mapped back to the "common" page zero. -- 40+yrs virtualization experience (since Jan68), online at home since Mar70 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
