On 11/3/2025 11:00 AM, Mitul Golani wrote:
Add function to check if DC Balance possibile on
requested PIPE and also validate along with DISPLAY_VER
check.
Signed-off-by: Mitul Golani <[email protected]>
Reviewed-by: Ankit Nautiyal <[email protected]>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index d68306cdbf57..50bb3a1f6105 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -236,6 +236,22 @@ void intel_vrr_compute_cmrr_timings(struct
intel_crtc_state *crtc_state)
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
+static
+int intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
+
+ /*
+ * FIXME: Currently Firmware supports DC Balancing on PIPE A
+ * and PIPE B. Account those limitation while computing DC
+ * Balance parameters.
+ */
+ return (HAS_VRR_DC_BALANCE(display) &&
+ ((pipe == PIPE_A) || (pipe == PIPE_B)));
Earlier there were plans to have this supported on other pipes, but now
I think this condition is fixed that only PIPE A/B have this feature. So
this change can be clubbed with the previous patch.
Regards,
Ankit
+}
+
static
void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state,
int vmin, int vmax)
@@ -249,7 +265,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state
*crtc_state,
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
- if (HAS_VRR_DC_BALANCE(display))
+ if (intel_vrr_dc_balance_possible(crtc_state))
crtc_state->vrr.dc_balance.enable = true;
}