Account for DSC slice overhead bubbles and adjust the pixel rate while checking the pixel rate against the max dotclock limits.
Signed-off-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 13 +++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.c | 1 - drivers/gpu/drm/i915/display/intel_vdsc.h | 3 +++ 5 files changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0acb3b64cf27..c1ff92367808 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1451,6 +1451,8 @@ bool intel_dp_can_join(struct intel_display *display, bool intel_dp_dotclk_valid(struct intel_display *display, int target_clock, + int htotal, + int dsc_slice_count, int num_joined_pipes) { int max_dotclk = display->cdclk.max_dotclk_freq; @@ -1458,6 +1460,12 @@ bool intel_dp_dotclk_valid(struct intel_display *display, effective_dotclk_limit = max_dotclk * num_joined_pipes; + if (dsc_slice_count) + target_clock = intel_dsc_get_pixel_rate_with_dsc_bubbles(display, + target_clock, + htotal, + dsc_slice_count); + return target_clock <= effective_dotclk_limit; } @@ -1592,8 +1600,13 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (status != MODE_OK) continue; + if (!dsc) + dsc_slice_count = 0; + if (intel_dp_dotclk_valid(display, target_clock, + mode->htotal, + dsc_slice_count, num_joined_pipes)) { status = MODE_OK; break; @@ -2827,6 +2840,7 @@ intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder, int max_dotclk = display->cdclk.max_dotclk_freq; struct link_config_limits limits; bool dsc_needed, joiner_needs_dsc; + int dsc_slice_count = 0; int ret = 0; joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes); @@ -2878,10 +2892,15 @@ intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder, return ret; } + if (pipe_config->dsc.compression_enable) + dsc_slice_count = intel_dsc_line_slice_count(&pipe_config->dsc.slice_config); + max_dotclk *= num_joined_pipes; if (!intel_dp_dotclk_valid(display, adjusted_mode->crtc_clock, + adjusted_mode->crtc_htotal, + dsc_slice_count, num_joined_pipes)) return -EINVAL; diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 78fa8eaba4ac..beef480b7672 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -230,6 +230,8 @@ bool intel_dp_can_join(struct intel_display *display, int num_joined_pipes); bool intel_dp_dotclk_valid(struct intel_display *display, int target_clock, + int htotal, + int dsc_slice_count, int num_joined_pipes); #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index f433a01dcfcb..bdf2f09fa03e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -702,6 +702,7 @@ static int mst_stream_compute_config(struct intel_encoder *encoder, pipe_config->has_pch_encoder = false; for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) { + int dsc_slice_count = 0; ret = -EINVAL; @@ -731,8 +732,12 @@ static int mst_stream_compute_config(struct intel_encoder *encoder, if (ret) continue; + dsc_slice_count = intel_dp_mst_dsc_get_slice_count(connector, pipe_config); + if (intel_dp_dotclk_valid(display, adjusted_mode->clock, + adjusted_mode->htotal, + dsc_slice_count, num_joined_pipes)) { ret = 0; break; @@ -1531,6 +1536,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, } for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) { + int dsc_slice_count = 0; *status = MODE_CLOCK_HIGH; @@ -1556,6 +1562,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, */ int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); + dsc_slice_count = intel_dp_dsc_get_slice_count(connector, + mode->clock, + mode->hdisplay, + num_joined_pipes); + if (!drm_dp_is_uhbr_rate(max_link_clock)) bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC; @@ -1580,6 +1591,8 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, if (intel_dp_dotclk_valid(display, mode->clock, + mode->htotal, + dsc_slice_count, num_joined_pipes)) { *status = MODE_OK; break; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 642a89270d8e..7e53201b3cb1 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -1104,7 +1104,6 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent, drm_dsc_dump_config(p, indent, &crtc_state->dsc.config); } -static int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display, int pixel_rate, int htotal, int dsc_horizontal_slices) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h index aeb17670307b..f4d5b37293cf 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h @@ -41,5 +41,8 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state); int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state); unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state); +int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display, + int pixel_rate, int htotal, + int dsc_horizontal_slices); #endif /* __INTEL_VDSC_H__ */ -- 2.45.2
