On Wed, Jan 28, 2026 at 07:36:32PM +0530, Ankit Nautiyal wrote: > Make dsc_slice_count closer to the block where it is used and promote it > from u8 to int. This aligns it with upcoming DSC bubble pixel-rate > adjustments, where the slice count participates in wider arithmetic. > > Currently, for non-eDP (DP/DP_MST) cases the slice count is computed only > inside intel_dp_dsc_mode_valid() and is not used by the caller. Once DSC > bubble handling is added, dp_mode_valid() will need access to its own local > slice count for non-eDP cases as well. > > Signed-off-by: Ankit Nautiyal <[email protected]>
Reviewed-by: Imre Deak <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++------- > 1 file changed, 6 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 655688c8e6ef..0acb3b64cf27 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1473,7 +1473,6 @@ intel_dp_mode_valid(struct drm_connector *_connector, > int target_clock = mode->clock; > int max_rate, mode_rate, max_lanes, max_link_clock; > u16 dsc_max_compressed_bpp = 0; > - u8 dsc_slice_count = 0; > enum drm_mode_status status; > bool dsc = false; > int num_joined_pipes; > @@ -1523,6 +1522,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, > * over candidate pipe counts and evaluate each combination. > */ > for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) { > + int dsc_slice_count = 0; > > status = MODE_CLOCK_HIGH; > > @@ -1547,6 +1547,11 @@ intel_dp_mode_valid(struct drm_connector *_connector, > if (intel_dp_has_dsc(connector)) { > int pipe_bpp; > > + dsc_slice_count = > intel_dp_dsc_get_slice_count(connector, > + > target_clock, > + > mode->hdisplay, > + > num_joined_pipes); > + > /* > * TBD pass the connector BPC, > * for now U8_MAX so that max BPC on that platform > would be picked > @@ -1561,12 +1566,6 @@ intel_dp_mode_valid(struct drm_connector *_connector, > dsc_max_compressed_bpp = > > drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; > > - dsc_slice_count = > - intel_dp_dsc_get_slice_count(connector, > - > target_clock, > - > mode->hdisplay, > - > num_joined_pipes); > - > dsc = dsc_max_compressed_bpp && dsc_slice_count; > } else if > (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { > unsigned long bw_overhead_flags = 0; > -- > 2.45.2 >
