Hi Matt
mattschinkel wrote:
>> Do these mode have commonly used names ? If so, it could be useful and
>> easier for users to provide procedures like spi_set_mode_indredible() or
>> spi_set_mode_amazing(), ... This would help to hide complexity (if it is a
>> good idea to hide complexity).
In my view hiding complexity is not always a good idea, but there is a
difference for 'normal' Jal users and library developers!
For the libraries we try to make the user interface identical for the
whole range of 8-bits PICs, but that doesn't mean we should make it
'ultimately' easy to use. Every additional procedure could require
another stack level. That may not be a problem for an 18F, but for the
midrange and even more for the baseline this could be disastrous. So
keep that in mind.
>
> the mode names are 0,0 0,1 1,0 and 1,1 as in this chart:
>
> -- SPI Mode Name - CKP CKE
> -- 0,0 - 0 1
> -- 0,1 - 0 0
> -- 1,0 - 1 1
> -- 1,1 - 1 0
>
> hence the original _spi_init_mode00
>
> The problem is that 16F877 uses these registers:
> SSPCON_CKP = 0 -- idle state for clock is high level
> SSPSTAT_CKE = 0 -- clock edge select, data transmitted on falling
>
> and 18F452 uses the following:
> SSP1CON_CKP = 0 -- idle state for clock is high level
> SSP1STAT_CKE = 0 -- clock edge select, data transmitted on falling
The normalisation of SSP registers is described in devicefiles.html. No
reason is given, but handling was expected to be significantly different
between midrange and 18Fs.
When this is for the SPI library the only difference between midrange an
18Fs
then a compile-time switch might be used, like in some other libraries.
if target_cpu == PIC_14 then -- midrange
SSPCON_CKP = 0 -- idle state for clock is high level
SSPSTAT_CKE = 0 -- clock edge select, data transmitted on falling
elsif target_cpu == PIC_16 then -- 18F series
SSP1CON_CKP = 0 -- idle state for clock is high level
SSP1STAT_CKE = 0 -- clock edge select, data transmitted on falling
end if
Regards, Rob.
--
Rob Hamerling, Vianen, NL (http://www.robh.nl/)
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