On Mon, May 10, 2010 at 12:46 PM, Florin Tanasa <[email protected]>wrote:
> Hi Vasi, > On Monday 10 May 2010 22:10:44 funlw65 wrote: > > Hi Florin, > > > > Be careful, test the 555 pulse generator on a breadboard first. It can > > be very noisy (at least SN7400N quadruple 2-input NAND gate, used by > > me as train pulse generator, it was). If you have too many pulses as > > normal then you must use an "optocoupler" between (or maybe using an > > 12F675 as pulse generator with a potmeter on an adc input to > > increasing/decreasing frequency?). > > > Thanks for the tips. > Hi all, > I change the schematic and now looks like easypic6 :) > Other opinions? > > > > I guess you're on the same boat with Vasi (looking at the pictures of wind rattle with romanian and EU flag on the tail...) Your schematic has too small fonts on VDD and VSS and is hard to read. If you want opinions, please edit your schematic in such manner it can be easily read. Vasile -- You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/jallib?hl=en.
