Hi Seb,

On 2011/04/02 19:22, Sebastien Lelong wrote:

Just a follow-up about setting PLL on 18F27J53. It works using "pragma
target PLLEN P4". And it also works using OSCTUNE register
(OSCTUNE_PLLEN = on).

I assume with "it works" you mean that with enabling PLL you also changed the 'pragma target clock xxxx' to match the resulting clock speed (to obtain a 2 Hz blinking LED). Well, that is the way it is supposed to work, isn't it?
If you mean something else please be more explicit

PLL requires 2ms before being stable. Clock
diagram in datasheet show a XOR gate between PLLEN fuse (termed CFGPLLEN
in datasheet) and OSCTUNE_PLLEN. But enabling both also works...
Finally, sample codes from Microchip doesn't use CFGPLLEN (fuse) but
prefer act on OSCTUNE_PLLEN.

Config bits are fixed, control registers may change during runtime. Some config bits settings can exclude (or include) the possibility to change control register bits (that is setting or resetting doesn't have effect). It is up to the designer of the program if he chooses one or the other method. For example when using a bootloader you probably prefer to use the control register method (provided the bootloader config bits settings allow you!).

Is it better to use OSCTUNE ? Can PLL be enabled at runtime ? (I read
something about differences with this chip regarding, but can't remember
what and where exactly). Should we do the same as Microchip ?

The datasheet (or programming specifications) are generally quite clear about the possibilities. But when you have a choice out of different possibilities for the same effect Microchip leaves the choice to the user and I like that. As far as the (generated) blink samples are concerned: I think it is better to use the same method for all chips if possible. Additional ('hand made') blink samples could be added for popular chips or for special conditions (and there are already several of these).

Regards, Rob.

--
R. Hamerling, Netherlands --- http://www.robh.nl

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