Add bindings for the System-0 clocks and reset generator (SYS0CRG) on JHB100 SoC.
Signed-off-by: Changhuang Liang <[email protected]> --- .../clock/starfive,jhb100-sys0crg.yaml | 63 +++++++++++++++++++ .../dt-bindings/clock/starfive,jhb100-crg.h | 56 +++++++++++++++++ .../dt-bindings/reset/starfive,jhb100-crg.h | 28 +++++++++ 3 files changed, 147 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml create mode 100644 include/dt-bindings/clock/starfive,jhb100-crg.h create mode 100644 include/dt-bindings/reset/starfive,jhb100-crg.h diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml new file mode 100644 index 000000000000..08016a61992c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-sys0crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-0 Clock and Reset Generator + +maintainers: + - Changhuang Liang <[email protected]> + +properties: + compatible: + const: starfive,jhb100-sys0crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (25 MHz) + - description: PLL0 + - description: PLL1 + - description: PLL2 + + clock-names: + items: + - const: osc + - const: pll0 + - const: pll1 + - const: pll2 + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive-jhb100-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@13000000 { + compatible = "starfive,jhb100-sys0crg"; + reg = <0x13000000 0x4000>; + clocks = <&osc>, <&pll0>, <&pll1>, + <&syspll 0>; + clock-names = "osc", "pll0", "pll1", "pll2"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h new file mode 100644 index 000000000000..24ef2663f05a --- /dev/null +++ b/include/dt-bindings/clock/starfive,jhb100-crg.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Changhuang Liang <[email protected]> + * + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ + +/* SYS0CRG clocks */ +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN 17 +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG 18 + +#define JHB100_SYS0CLK_PCIE_REF_CML 20 +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_DATA_INIT 21 +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG_INIT 22 +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_TARG 23 + +#define JHB100_SYS0CLK_BMCPCIERP_PCU 26 +#define JHB100_SYS0CLK_HOSTSS0_NCNOC_CFG 27 +#define JHB100_SYS0CLK_HOSTSS0_NCNOC_DATA 28 +#define JHB100_SYS0CLK_HOSTSS0_PHY_SCAN_400 29 +#define JHB100_SYS0CLK_GPIO_ESPI0_EXT 30 + +#define JHB100_SYS0CLK_BMCUSB_NCNOC_INIT 34 +#define JHB100_SYS0CLK_BMCUSB_NCNOC_TARG 35 +#define JHB100_SYS0CLK_BMCUSB_SCANCLK 36 +#define JHB100_SYS0CLK_BMCUSB_480M_SCANCLK 37 + +#define JHB100_SYS0CLK_VCE_NCNOC_INIT 50 +#define JHB100_SYS0CLK_VCE_NCNOC_TARG 51 +#define JHB100_SYS0CLK_BMCPER2_NCNOC_INIT 52 +#define JHB100_SYS0CLK_BMCPER2_NCNOC_TARG 53 +#define JHB100_SYS0CLK_BMCPER2_CFG_400 54 +#define JHB100_SYS0CLK_BMCPER2_CFG_125 55 + +#define JHB100_SYS0CLK_HOSTSS1_NCNOC_DATA 58 +#define JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400 59 +#define JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400_ICG_BUF 60 +#define JHB100_SYS0CLK_NPU_NCNOC_INIT 61 +#define JHB100_SYS0CLK_VOUT_NCNOC_INIT 62 +#define JHB100_SYS0CLK_VOUT_AUX 63 + +#define JHB100_SYS0CLK_BMCPER3_NCNOC_INIT 65 +#define JHB100_SYS0CLK_HOSTUSB_NCNOC_INIT 66 +#define JHB100_SYS0CLK_HOSTUSBCMN_CFG_480 67 +#define JHB100_SYS0CLK_BMCPER1_NCNOC_INIT 68 +#define JHB100_SYS0CLK_BMCPER1_CFG_800 69 +#define JHB100_SYS0CLK_BMCPER0_NCNOC_INIT 70 +#define JHB100_SYS0CLK_BMCPER0_CFG_400 71 +#define JHB100_SYS0CLK_BMCPER0_CFG_800 72 +#define JHB100_SYS0CLK_GPU0_NCNOC_INIT 73 +#define JHB100_SYS0CLK_GPU1_NCNOC_INIT 74 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h new file mode 100644 index 000000000000..5c7b00afda73 --- /dev/null +++ b/include/dt-bindings/reset/starfive,jhb100-crg.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Changhuang Liang <[email protected]> + * + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ + +/* SYS0CRG resets */ +#define JHB100_SYS0RST_RESOURCE_ARB 0 +#define JHB100_SYS0RST_SYS0_IOMUX_PRESETN 1 +#define JHB100_SYS0RST_SYS0H_IOMUX_PRESETN 2 +#define JHB100_SYS0RST_RST_ADAPTOR_TIMEOUT_RSTN 3 +#define JHB100_SYS0RST_BMCPCIERP_RSTN_BUS 4 +#define JHB100_SYS0RST_BMCPCIERP_RSTN_CRG 5 +#define JHB100_SYS0RST_HOSTSS0_RSTN_BUS_ESPI 6 +#define JHB100_SYS0RST_HOSTSS0_RSTN_BUS_PCIE 7 +#define JHB100_SYS0RST_HOSTSS0_RSTN_CRG 8 +#define JHB100_SYS0RST_BMCPERIPH2_RSTN_CRG 9 +#define JHB100_SYS0RST_BMCPERIPH2_RSTN_BUS 10 +#define JHB100_SYS0RST_VCE_RSTN_CRG 11 +#define JHB100_SYS0RST_VCE_RSTN_BUS 12 +#define JHB100_SYS0RST_BMCUSB_RSTN_BUS 13 +#define JHB100_SYS0RST_BMCUSB_RSTN_CRG 14 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */ -- 2.25.1
