Add clocks and resets nodes for JHB100 RISC-V BMC SoC. They contain sys0crg/sys1crg/sys2crg/per0crg/per1crg/per2crg/per3crg.
Signed-off-by: Changhuang Liang <[email protected]> --- arch/riscv/boot/dts/starfive/jhb100.dtsi | 198 ++++++++++++++++++++++- 1 file changed, 195 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi index 4133ba1f45b4..943324b3b2fd 100644 --- a/arch/riscv/boot/dts/starfive/jhb100.dtsi +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi @@ -4,6 +4,8 @@ */ /dts-v1/; +#include <dt-bindings/clock/starfive,jhb100-crg.h> +#include <dt-bindings/reset/starfive,jhb100-crg.h> / { compatible = "starfive,jhb100"; @@ -268,12 +270,96 @@ pmu { <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */ }; - clk_uart: clock-25000000 { - compatible = "fixed-clock"; /* Initial clock handler for UART */ + osc: clock-osc { + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; + pll0: clock-pll0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2400000000>; + }; + + pll1: clock-pll1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + pll2: clock-pll2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <903168000>; + }; + + pll4: clock-pll4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100700000>; + }; + + pll5: clock-pll5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100700000>; + }; + + pll6: clock-pll6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2400000000>; + }; + + pll7: clock-pll7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1950000000>; + }; + + per2_gmac2_rgmii_rx: clock-per2-gmac2-rgmii-rx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + per2_gmac2_rmii_ref: clock-per2-gmac2-rmii-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + per2_gmac3_sgmii_tx: clock-per2-gmac3-sgmii-tx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + per2_gmac3_sgmii_rx: clock-per2-gmac3-sgmii-rx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + per3_gmac0_rmii_rclki: clock-per3-gmac0-rmii-rclki { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + per3_gmac1_sgmii_tx: clock-per3-gmac1-sgmii-tx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + per3_gmac1_sgmii_rx: clock-per3-gmac1-sgmii-rx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -316,8 +402,10 @@ bus_nioc: bus_nioc { uart6: serial@11982000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x11982000 0x0 0x400>; - clocks = <&clk_uart>, <&clk_uart>; + clocks = <&per0crg JHB100_PER0CLK_SCLK_UART6>, + <&per0crg JHB100_PER0CLK_APB_UART6>; clock-names = "baudclk", "apb_pclk"; + resets = <&per0crg JHB100_PER0RST_MAIN_RSTN_UART6>; interrupt-parent = <&intc>; interrupts = <26>; reg-io-width = <4>; @@ -325,6 +413,110 @@ uart6: serial@11982000 { status = "disabled"; }; + per0crg: clock-controller@11a08000 { + compatible = "starfive,jhb100-per0crg"; + reg = <0x0 0x11a08000 0x0 0x1000>; + clocks = <&osc>, <&pll6>, + <&sys0crg JHB100_SYS0CLK_BMCPER0_CFG_400>, + <&sys0crg JHB100_SYS0CLK_BMCPER0_CFG_800>, + <&sys0crg JHB100_SYS0CLK_BMCPER0_NCNOC_INIT>, + <&sys2crg JHB100_SYS2CLK_BMCPER0_NCNOC_TARG>; + clock-names = "osc", "pll6", "cfg_400", + "cfg_800", "ncnoc_init", + "ncnoc_targ"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + per1crg: clock-controller@11b40000 { + compatible = "starfive,jhb100-per1crg"; + reg = <0x0 0x11b40000 0x0 0x1000>; + clocks = <&pll7>, + <&sys0crg JHB100_SYS0CLK_BMCPER1_NCNOC_INIT>, + <&sys0crg JHB100_SYS0CLK_BMCPER1_CFG_800>, + <&sys2crg JHB100_SYS2CLK_BMCPER1_NCNOC_TARG>, + <&sys2crg JHB100_SYS2CLK_BMCPER1_CFG_143>; + clock-names = "pll7", "ncnoc_init", + "cfg_800", "ncnoc_targ", + "cfg_143"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + per2crg: clock-controller@11bc0000 { + compatible = "starfive,jhb100-per2crg"; + reg = <0x0 0x11bc0000 0x0 0x1000>; + clocks = <&sys0crg JHB100_SYS0CLK_BMCPER2_NCNOC_INIT>, + <&sys0crg JHB100_SYS0CLK_BMCPER2_CFG_400>, + <&sys0crg JHB100_SYS0CLK_BMCPER2_CFG_125>, + <&per2_gmac2_rgmii_rx>, + <&per2_gmac2_rmii_ref>, + <&per2_gmac3_sgmii_tx>, + <&per2_gmac3_sgmii_rx>, + <&osc>; + clock-names = "ncnoc_init", "cfg_400", "cfg_125", + "gmac2_rgmii_rx", + "gmac2_rmii_ref", + "gmac3_sgmii_tx", + "gmac3_sgmii_rx", + "osc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + per3crg: clock-controller@11c40000 { + compatible = "starfive,jhb100-per3crg"; + reg = <0x0 0x11c40000 0x0 0x1000>; + clocks = <&sys0crg JHB100_SYS0CLK_BMCPER3_NCNOC_INIT>, + <&sys1crg JHB100_SYS1CLK_BMCPER3_NCNOC_TARG>, + <&sys1crg JHB100_SYS1CLK_BMCPER3_CFG_125>, + <&per3_gmac0_rmii_rclki>, + <&per3_gmac1_sgmii_tx>, + <&per3_gmac1_sgmii_rx>, + <&osc>; + clock-names = "ncnoc_init", "ncnoc_targ", "cfg_125", + "gmac0_rmii_rclki", + "gmac1_sgmii_tx", + "gmac1_sgmii_rx", + "osc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + sys0crg: clock-controller@13000000 { + compatible = "starfive,jhb100-sys0crg"; + reg = <0x0 0x13000000 0x0 0x4000>; + clocks = <&osc>, <&pll0>, <&pll1>, + <&pll2>; + clock-names = "osc", "pll0", "pll1", "pll2"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + sys1crg: clock-controller@13004000 { + compatible = "starfive,jhb100-sys1crg"; + reg = <0x0 0x13004000 0x0 0x4000>; + clocks = <&osc>, <&pll0>, <&pll1>, + <&pll2>, <&pll4>, <&pll5>, + <&sys0crg JHB100_SYS0CLK_NPU_NCNOC_INIT>; + clock-names = "osc", "pll0", "pll1", "pll2", + "pll4", "pll5", "npu_ncnoc_init"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + sys2crg: clock-controller@13008000 { + compatible = "starfive,jhb100-sys2crg"; + reg = <0x0 0x13008000 0x0 0x4000>; + clocks = <&osc>, <&pll1>, + <&sys0crg JHB100_SYS0CLK_GPU0_NCNOC_INIT>, + <&sys0crg JHB100_SYS0CLK_GPU1_NCNOC_INIT>; + clock-names = "osc", "pll1", "gpu0_ncnoc_init", + "gpu1_ncnoc_init"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + intc: interrupt-controller@13220000 { compatible = "starfive,jhb100-intc"; reg = <0x0 0x13220000 0x0 0x80>; -- 2.25.1
